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Message-Id: <5B0421E502000078001C4B91@prv1-mh.provo.novell.com>
Date: Tue, 22 May 2018 07:57:57 -0600
From: "Jan Beulich" <JBeulich@...e.com>
To: <brgerst@...il.com>
Cc: "xen-devel" <xen-devel@...ts.xenproject.org>,
"Boris Ostrovsky" <boris.ostrovsky@...cle.com>,
"Juergen Gross" <jgross@...e.com>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 1/2] xen/PVH: Set up GS segment for stack canary
>>> On 22.05.18 at 15:45, <brgerst@...il.com> wrote:
> On Mon, May 21, 2018 at 11:54 PM, Boris Ostrovsky <boris.ostrovsky@...cle.com> wrote:
>> @@ -98,6 +101,12 @@ ENTRY(pvh_start_xen)
>> /* 64-bit entry point. */
>> .code64
>> 1:
>> + /* Set base address in stack canary descriptor. */
>> + mov $MSR_GS_BASE,%ecx
>> + mov $canary, %rax
>> + cdq
>> + wrmsr
>
> CDQ only sign-extends EAX to RAX. What you really want is to move the
> high 32-bits to EDX (or zero EDX if we can guarantee it is loaded
> below 4G).
What you describe is CDQE (AT&T name: CLTD); CDQ (AT&T: CLTQ)
sign-extends EAX to EDX:EAX.
Jan
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