linux-kernel - Re: [PATCH v3 13/16] mtd: rawnand: qcom: minor code reorganization for bad block check

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Message-ID: <20180528090931.4a208c62@xps13>
Date:   Mon, 28 May 2018 09:09:31 +0200
From:   Miquel Raynal <miquel.raynal@...tlin.com>
To:     Abhishek Sahu <absahu@...eaurora.org>
Cc:     Boris Brezillon <boris.brezillon@...tlin.com>,
        David Woodhouse <dwmw2@...radead.org>,
        Brian Norris <computersforpeace@...il.com>,
        Marek Vasut <marek.vasut@...il.com>,
        Richard Weinberger <richard@....at>,
        Cyrille Pitchen <cyrille.pitchen@...ev4u.fr>,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-mtd@...ts.infradead.org, Andy Gross <andy.gross@...aro.org>,
        Archit Taneja <architt@...eaurora.org>
Subject: Re: [PATCH v3 13/16] mtd: rawnand: qcom: minor code reorganization
 for bad block check

Hi Abhishek,

On Mon, 28 May 2018 11:46:47 +0530, Abhishek Sahu
<absahu@...eaurora.org> wrote:

> On 2018-05-26 14:28, Miquel Raynal wrote:
> > Hi Abhishek,  
> > > >> @@ -2141,12 +2127,10 @@ static int qcom_nandc_block_bad(struct >> mtd_info *mtd, loff_t ofs)  
> >>  		goto err;
> >>  	}  
> >> >> -	bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);  
> >> -
> >> -	bad = nandc->data_buffer[bbpos] != 0xff;
> >> +	bad = bbm_bytes_buf[0] != 0xff;
> > > BTW, as there are host->bbm_size bytes that can inform on the block  
> > state, don't we need to check all of them?
> >   
>   We are checking all of them.
>   host->bbm_size will be either 1 (for NAND_BUSWIDTH_8) or
>   2 (for NAND_BUSWIDTH_16).
> 
>   https://elixir.bootlin.com/linux/v4.17-rc7/source/drivers/mtd/nand/raw/qcom_nandc.c#L2347
> 
>   Thanks,
>   Abhishek
> 
> >> >>  	if (chip->options & NAND_BUSWIDTH_16)  
> >> -		bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff);
> >> +		bad = bad || (bbm_bytes_buf[1] != 0xff);

As told in my previous reply, I missed the above line.

However, after checking the code of the core (nand_base.c) I wonder if
it is useful to check for the second byte.

And if you look at the core's implementation you'll see that the offset
is not always 0 in the OOB but maybe 5 for small page NAND chips.

Please have a look to the generic implementation and tell me why this
is really needed?

Thanks,
Miquèl