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Message-ID: <CAHQ1cqE9dpL3DB351UbjWvh+g=BG62NP31iqoOsPm_9_tKS0sQ@mail.gmail.com>
Date: Tue, 29 May 2018 16:16:49 -0700
From: Andrey Smirnov <andrew.smirnov@...il.com>
To: Leonard Crestez <leonard.crestez@....com>
Cc: Anson Huang <Anson.Huang@....com>, Shawn Guo <shawnguo@...nel.org>,
Linux-imx@....com,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Sascha Hauer <kernel@...gutronix.de>,
Fabio Estevam <fabio.estevam@....com>,
Abel Vesa <abel.vesa@....com>,
Richard Liu <xuegang.liu@....com>
Subject: Re: [PATCH] soc: imx: gpcv2: correct PGC offset
On Tue, May 29, 2018 at 7:02 AM, Leonard Crestez
<leonard.crestez@....com> wrote:
> On Tue, 2018-05-29 at 16:02 +0800, Anson Huang wrote:
>> Correct MIPI/PCIe/USB_HSIC's PGC offset based on
>> design RTL, the value on Reference Manual are incorrect.
>>
>> The correct offset should be as below:
>>
>> -#define PGC_MIPI 4
>> -#define PGC_PCIE 5
>> -#define PGC_USB_HSIC 8
>> +#define PGC_MIPI 16
>> +#define PGC_PCIE 17
>> +#define PGC_USB_HSIC 20
>> #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
>> #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
>
> This gpcv2 driver is currently only used for PCI, it probably only
> works because domains happen to be turned on by default?
>
That'd be my guess as well. I just tried commenting all of the code
related to GPC_PGC_CTRL in gpcv2 drive and PCIe still worked on my
SabreSD board.
> On imx7d upstream platform suspend is not yet supported but even doing
> device-level suspend causes a hang on resume somewhere in PCI on first
> read. This patch fixes that immediate hang.
>
> After suspend/resume lspci is broken (device doesn't properly resume),
> that probably requires more imx pci patches and unrelated to pgc.
>
Yeah, suspend of any kind was not a part of the use-case for me when I
was working on this driver, so it's not surprising to hear that it
doesn't work very well.
Thanks,
Andrey Smirnov
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