linux-kernel - Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

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Message-ID: <04cdfdf5-33c5-b569-9cd7-dda1b9ea0baf@gmail.com>
Date:   Tue, 29 May 2018 15:19:47 +0300
From:   Dmitry Osipenko <digetx@...il.com>
To:     Stefan Agner <stefan@...er.ch>,
        Peter De Schrijver <pdeschrijver@...dia.com>
Cc:     boris.brezillon@...tlin.com, dwmw2@...radead.org,
        computersforpeace@...il.com, marek.vasut@...il.com,
        robh+dt@...nel.org, mark.rutland@....com, thierry.reding@...il.com,
        mturquette@...libre.com, sboyd@...nel.org, dev@...xeye.de,
        miquel.raynal@...tlin.com, richard@....at, marcel@...wiler.com,
        krzk@...nel.org, benjamin.lindqvist@...ian.se,
        jonathanh@...dia.com, pgaikwad@...dia.com, mirza.krak@...il.com,
        linux-mtd@...ts.infradead.org, linux-tegra@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On 29.05.2018 15:12, Stefan Agner wrote:
> On 29.05.2018 09:48, Peter De Schrijver wrote:
>> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
>>> On 28.05.2018 09:55, Peter De Schrijver wrote:
>>>> On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>>>>> From: Lucas Stach <dev@...xeye.de>
>>>>>
>>>>> Set up the NAND Flash controller clock to run at 150MHz
>>>>> instead of the rate set by the bootloader. This is a
>>>>> conservative rate which also yields good performance.
>>>>>
>>>>> Signed-off-by: Lucas Stach <dev@...xeye.de>
>>>>> Signed-off-by: Stefan Agner <stefan@...er.ch>
>>>>> ---
>>>>>  drivers/clk/tegra/clk-tegra20.c | 1 +
>>>>>  1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
>>>>> index 0ee56dd04cec..dff8c425cd28 100644
>>>>> --- a/drivers/clk/tegra/clk-tegra20.c
>>>>> +++ b/drivers/clk/tegra/clk-tegra20.c
>>>>> @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
>>>>>  	{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
>>>>>  	{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
>>>>>  	{ TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },
>>>>> +	{ TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0 },
>>>>>  	/* must be the last entry */
>>>>>  	{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
>>>>>  };
>>>>> --
>>>>> 2.17.0
>>>>>
>>>>
>>>> Maybe better to specify this in the Tegra20 dtsi? See
>>>> "Assigned clock parents and rates" in
>>>> Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>
>>> assigned-clocks indeed works just fine for this case. Thanks for
>>> bringing this up, will drop this patch and add the device tree
>>> properties in v3.
>>>
>>> Hm, interesting that none of the Tegra device tree make use of the
>>> feature so far. I guess there would be other cases where this would be
>>> useful as well (the one just above, VDE?).
>>>
>>
>> Yes, historically this feature wasn't available, so we used these init tables.
>> Unfortunately it's not easy to get rid of them for parent and rate
>> configuration, because new kernels should also work with existing DTBs, so we
>> can't just add assigned-clock properties and remove the existing table
>> entries. What we could do is use the CLK_IS_CRITICAL flag for all clocks which
>> are only enabled by the init table. For not yet merged blocks, this is
>> ofcourse not a concern.
> 
> Sure I understand.
> 
> Was just somewhat surprised that it isn't used at all yet (grep -r -e
> assigned-clock arch/arm/boot/dts/tegra* returns nothing). After all,
> assigned clocks bindings have been merged in 2014 :-)
> 
> At least "clk: tegra: Specify VDE clock rate" merged earlier this year
> would have been a candidate already.

I wasn't even aware of existence of the assigned-clock properties, probably just
like others.