linux-kernel - Re: [PATCH v10 0/2] Initial Allwinner V3s CSI Support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20180530091934.tbd6xbyr5s3ipn3v@paasikivi.fi.intel.com>
Date:   Wed, 30 May 2018 12:19:34 +0300
From:   Sakari Ailus <sakari.ailus@...ux.intel.com>
To:     Maxime Ripard <maxime.ripard@...tlin.com>
Cc:     Yong Deng <yong.deng@...ewell.com>,
        Hans Verkuil <hans.verkuil@...co.com>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Chen-Yu Tsai <wens@...e.org>,
        "David S. Miller" <davem@...emloft.net>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Randy Dunlap <rdunlap@...radead.org>,
        Arnd Bergmann <arnd@...db.de>,
        Stanimir Varbanov <stanimir.varbanov@...aro.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Ramesh Shanmugasundaram <ramesh.shanmugasundaram@...renesas.com>,
        Jacob Chen <jacob-chen@...wrt.com>,
        Yannick Fertre <yannick.fertre@...com>,
        Thierry Reding <treding@...dia.com>,
        Benjamin Gaignard <benjamin.gaignard@...aro.org>,
        Todor Tomov <todor.tomov@...aro.org>,
        linux-media@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-sunxi@...glegroups.com
Subject: Re: [PATCH v10 0/2] Initial Allwinner V3s CSI Support

On Tue, May 29, 2018 at 11:57:57AM +0200, Maxime Ripard wrote:
> On Thu, May 17, 2018 at 11:02:24AM +0200, Maxime Ripard wrote:
> > On Fri, May 04, 2018 at 02:44:08PM +0800, Yong Deng wrote:
> > > This patchset add initial support for Allwinner V3s CSI.
> > > 
> > > Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2
> > > interface and CSI1 is used for parallel interface. This is not
> > > documented in datasheet but by test and guess.
> > > 
> > > This patchset implement a v4l2 framework driver and add a binding 
> > > documentation for it. 
> > > 
> > > Currently, the driver only support the parallel interface. And has been
> > > tested with a BT1120 signal which generating from FPGA. The following
> > > fetures are not support with this patchset:
> > >   - ISP 
> > >   - MIPI-CSI2
> > >   - Master clock for camera sensor
> > >   - Power regulator for the front end IC
> > 
> > I tested it on my H3 with a parallel camera, and it still works. Thanks!
> > 
> > Hans, Sakari, any chance this might land in 4.18?
> 
> Ping?

I'll try to look into this soonish but it seems to be too late for 4.18.
Sorry about that.

-- 
Sakari Ailus
sakari.ailus@...ux.intel.com