linux-kernel - Re: [PATCH V2] soc: imx: gpcv2: correct PGC offset

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Message-ID: <CAOMZO5CBgrtKpGdknpwOFbdOR219JqfVJnOeEjdL1a1GiBdg=g@mail.gmail.com>
Date:   Wed, 30 May 2018 09:50:42 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     Anson Huang <Anson.Huang@....com>
Cc:     Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Sascha Hauer <kernel@...gutronix.de>,
        Fabio Estevam <fabio.estevam@....com>,
        Andrey Smirnov <andrew.smirnov@...il.com>,
        NXP Linux Team <Linux-imx@....com>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2] soc: imx: gpcv2: correct PGC offset

Hi Anson,

On Tue, May 29, 2018 at 10:30 PM, Anson Huang <Anson.Huang@....com> wrote:
> Correct MIPI/PCIe/USB_HSIC's PGC offset based on
> design RTL, the values in the Reference Manual
> (Rev. 1, 01/2018 and the older ones) are incorrect.
>
> The correct offset values should be as below:
>
> 0x800 ~ 0x83F: PGC for core0 of A7 platform;
> 0x840 ~ 0x87F: PGC for core1 of A7 platform;
> 0x880 ~ 0x8BF: PGC for SCU of A7 platform;
> 0xA00 ~ 0xA3F: PGC for fastmix/megamix;
> 0xC00 ~ 0xC3F: PGC for MIPI PHY;
> 0xC40 ~ 0xC7F: PGC for PCIe_PHY;
> 0xC80 ~ 0xCBF: PGC for USB OTG1 PHY;
> 0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY;
> 0xD00 ~ 0xD3F: PGC for USB HSIC PHY;
>
> Signed-off-by: Anson Huang <Anson.Huang@....com>
> Acked-by: Andrey Smirnov <andrew.smirnov@...il.com>

Thanks for the fix:

Reviewed-by: Fabio Estevam <fabio.estevam@....com>