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Message-Id: <1527856758-27169-3-git-send-email-cpandya@codeaurora.org>
Date: Fri, 1 Jun 2018 18:09:15 +0530
From: Chintan Pandya <cpandya@...eaurora.org>
To: will.deacon@....com, catalin.marinas@....com, mark.rutland@....com,
akpm@...ux-foundation.org
Cc: toshi.kani@....com, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Chintan Pandya <cpandya@...eaurora.org>
Subject: [PATCH v12 2/5] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable
Add an interface to invalidate intermediate page tables
from TLB for kernel.
Signed-off-by: Chintan Pandya <cpandya@...eaurora.org>
---
arch/arm64/include/asm/tlbflush.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index dfc61d7..a4a1901 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -218,6 +218,13 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
dsb(ish);
}
+static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
+{
+ unsigned long addr = __TLBI_VADDR(kaddr, 0);
+
+ __tlbi(vaae1is, addr);
+ dsb(ish);
+}
#endif
#endif
--
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