linux-kernel - [alsa-devel][PATCH 3/3] ASoC: TSCS42xx: Add headphone auto switching

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Message-ID: <cec911cd9111bb4ae25bb9ec2df3af134bc49c58.1528143829.git.steven.eckhoff.opensource@gmail.com>
Date:   Mon, 4 Jun 2018 15:47:02 -0500
From:   Steven Eckhoff <steven.eckhoff.opensource@...il.com>
To:     alsa-devel@...a-project.org
Cc:     Steven Eckhoff <steven.eckhoff.opensource@...il.com>,
        Liam Girdwood <lgirdwood@...il.com>,
        Mark Brown <broonie@...nel.org>,
        Jaroslav Kysela <perex@...ex.cz>,
        Takashi Iwai <tiwai@...e.com>, alsa-devel@...a-project.org,
        linux-kernel@...r.kernel.org
Subject: [alsa-devel][PATCH 3/3] ASoC: TSCS42xx: Add headphone auto switching

Add headphone auto switching controls

Signed-off-by: Steven Eckhoff <steven.eckhoff.opensource@...il.com>
---
 sound/soc/codecs/tscs42xx.c | 6 ++++++
 sound/soc/codecs/tscs42xx.h | 8 ++++++++
 2 files changed, 14 insertions(+)

diff --git a/sound/soc/codecs/tscs42xx.c b/sound/soc/codecs/tscs42xx.c
index c79c075228a6..4f56d2937a35 100644
--- a/sound/soc/codecs/tscs42xx.c
+++ b/sound/soc/codecs/tscs42xx.c
@@ -641,6 +641,12 @@ static const struct snd_kcontrol_new tscs42xx_snd_controls[] = {
 	/* Mic Bias */
 	SOC_SINGLE("Mic Bias Boost Switch", 0x71, 0x07, 1, 0),
 
+	/* Headphone Auto Switching */
+	SOC_SINGLE("Headphone Auto Switching Switch",
+			R_CTL, FB_CTL_HPSWEN, 1, 0),
+	SOC_SINGLE("Headphone Detect Polarity Toggle Switch",
+			R_CTL, FB_CTL_HPSWPOL, 1, 0),
+
 	/* Coefficient Ram */
 	COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00),
 	COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05),
diff --git a/sound/soc/codecs/tscs42xx.h b/sound/soc/codecs/tscs42xx.h
index d4a30bcbf64b..9b15bf89c4d0 100644
--- a/sound/soc/codecs/tscs42xx.h
+++ b/sound/soc/codecs/tscs42xx.h
@@ -34,6 +34,7 @@ enum {
 #define R_DACSR         0x19
 #define R_PWRM1         0x1A
 #define R_PWRM2         0x1B
+#define R_CTL		0x1C
 #define R_CONFIG0       0x1F
 #define R_CONFIG1       0x20
 #define R_DMICCTL       0x24
@@ -1110,6 +1111,13 @@ enum {
 #define RV_PWRM2_VREF_DISABLE \
 	 RV(FV_PWRM2_VREF_DISABLE, FB_PWRM2_VREF)
 
+/******************************
+ *      R_CTL (0x1C)          *
+ ******************************/
+
+/* Fiel Offsets */
+#define FB_CTL_HPSWEN                        7
+#define FB_CTL_HPSWPOL                       6
 
 /******************************
  *      R_CONFIG0 (0x1F)      *
-- 
2.17.0