linux-kernel - Re: [PATCH 4/8] serial: 8250: Handle case port doesn't have TEMT interrupt using em485.

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Date:   Mon, 04 Jun 2018 14:38:58 +0300
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Giulio Benetti <giulio.benetti@...ronovasrl.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc:     Jiri Slaby <jslaby@...e.com>, Kees Cook <keescook@...omium.org>,
        Matthias Brugger <mbrugger@...e.com>,
        Allen Pais <allen.lkml@...il.com>, Sean Young <sean@...s.org>,
        Ed Blake <ed.blake@...drel.com>,
        Stefan Potyra <Stefan.Potyra@...ktrobit.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Joshua Scott <joshua.scott@...iedtelesis.co.nz>,
        Vignesh R <vigneshr@...com>,
        Rolf Evers-Fischer <rolf.evers.fischer@...iv.com>,
        Aaron Sierra <asierra@...-inc.com>,
        Rafael Gago <rafael.gago@...il.com>,
        Joel Stanley <joel@....id.au>,
        Sean Wang <sean.wang@...iatek.com>,
        linux-serial@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 4/8] serial: 8250: Handle case port doesn't have TEMT
 interrupt using em485.

On Mon, 2018-06-04 at 12:50 +0200, Giulio Benetti wrote:
> Hi,
> 
> Il 04/06/2018 12:17, Andy Shevchenko ha scritto:
> > On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
> > > Some 8250 ports only have TEMT interrupt, so current
> > > implementation
> > > can't work for ports without it. The only chance to make it work
> > > is to
> > > loop-read on LSR register.
> > > 
> > > With NO TEMT interrupt check if both TEMT and THRE are set looping
> > > on
> > > LSR register.
> > > --- a/drivers/tty/serial/8250/8250_dw.c
> > > +++ b/drivers/tty/serial/8250/8250_dw.c
> > > -		int ret = serial8250_em485_init(up);
> > > +		int ret = serial8250_em485_init(up, false);
> > 
> > Is true for all possible DW configured types? Or it's your
> > particular
> > case?
> > 
> 
> I've checked on Synopsis Designware 8250 datasheet and it's not
> supported.
> Here is datasheet I went through:
> https://linux-sunxi.org/images/d/d2/Dw_apb_uart_db.pdf
> 
> There seems not to be TEMT interrupt, I use it under sunxi SoC and on 
> their datasheet(A20 for example), they don't report that interrupt
> too.
> So it seems to be valid for all DW configured types, anyway I don't
> know 
> how many IP reviews there could be of that peripheral.

This is an excerpt from the document you referred to:

--- 8< --- 8< ---

6 TEMT R Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and
FIFOs enabled (FCR[0] set to one), this bit is set whenever the
Transmitter Shift Register and the FIFO are both empty. If in non-FIFO
mode or FIFOs are disabled, this bit is set whenever the Transmitter
Holding Register and the Transmitter Shift Register are both empty.

Reset Value: 0x1

--- 8< --- 8< ---


If I'm reading this correctly the support is there. Or otherwise, care
to point exact paragraph needs to be read and checked?

> I've tried to subscribe at Synopsis to obtain latest Datasheet but it 
> ask me an active ID I don't have.
> 

-- 
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Intel Finland Oy