linux-kernel - Re: [PATCH V2 2/4] mmc: sdhci-msm: Add msm version specific ops and data structures

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 6 Jun 2018 09:31:06 +0300
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Vijay Viswanath <vviswana@...eaurora.org>, ulf.hansson@...aro.org,
        robh+dt@...nel.org, mark.rutland@....com
Cc:     linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        shawn.lin@...k-chips.com, linux-arm-msm@...r.kernel.org,
        georgi.djakov@...aro.org, devicetree@...r.kernel.org,
        asutoshd@...eaurora.org, stummala@...eaurora.org,
        venkatg@...eaurora.org, jeremymc@...hat.com,
        bjorn.andersson@...aro.org, riteshh@...eaurora.org,
        vbadigan@...eaurora.org, dianders@...gle.com,
        sayalil@...eaurora.org
Subject: Re: [PATCH V2 2/4] mmc: sdhci-msm: Add msm version specific ops and
 data structures

On 29/05/18 12:52, Vijay Viswanath wrote:
> In addition to offsets of certain registers changing, the registers in
> core_mem have been shifted to HC mem as well. To access these
> registers, define msm version specific functions. These functions can
> be loaded into the function pointers at the time of probe based on
> the msm version detected.
> 
> Also defind new data structure to hold version specific Ops and
> register addresses.
> 
> Signed-off-by: Sayali Lokhande <sayalil@...eaurora.org>
> Signed-off-by: Vijay Viswanath <vviswana@...eaurora.org>

Acked-by: Adrian Hunter <adrian.hunter@...el.com>

> ---
>  drivers/mmc/host/sdhci-msm.c | 77 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 77 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 4050c99..2a66aa0 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -226,6 +226,24 @@ struct sdhci_msm_offset {
>  	.core_ddr_config_2 = 0x1bc,
>  };
>  
> +struct sdhci_msm_variant_ops {
> +	u8 (*msm_readb_relaxed)(struct sdhci_host *host, u32 offset);
> +	u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
> +	void (*msm_writeb_relaxed)(u8 val, struct sdhci_host *host, u32 offset);
> +	void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
> +			u32 offset);
> +};
> +
> +/*
> + * From V5, register spaces have changed. Wrap this info in a structure
> + * and choose the data_structure based on version info mentioned in DT.
> + */
> +struct sdhci_msm_variant_info {
> +	bool mci_removed;
> +	const struct sdhci_msm_variant_ops *var_ops;
> +	const struct sdhci_msm_offset *offset;
> +};
> +
>  struct sdhci_msm_host {
>  	struct platform_device *pdev;
>  	void __iomem *core_mem;	/* MSM SDCC mapped address */
> @@ -245,8 +263,45 @@ struct sdhci_msm_host {
>  	wait_queue_head_t pwr_irq_wait;
>  	bool pwr_irq_flag;
>  	u32 caps_0;
> +	bool mci_removed;
> +	const struct sdhci_msm_variant_ops *var_ops;
> +	const struct sdhci_msm_offset *offset;
>  };
>  
> +/*
> + * APIs to read/write to vendor specific registers which were there in the
> + * core_mem region before MCI was removed.
> + */
> +static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
> +		u32 offset)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
> +
> +	return readl_relaxed(msm_host->core_mem + offset);
> +}
> +
> +static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
> +		u32 offset)
> +{
> +	return readl_relaxed(host->ioaddr + offset);
> +}
> +
> +static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
> +		struct sdhci_host *host, u32 offset)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
> +
> +	writel_relaxed(val, msm_host->core_mem + offset);
> +}
> +
> +static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
> +		struct sdhci_host *host, u32 offset)
> +{
> +	writel_relaxed(val, host->ioaddr + offset);
> +}
> +
>  static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
>  						    unsigned int clock)
>  {
> @@ -1481,6 +1536,28 @@ static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
>  	pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
>  }
>  
> +static const struct sdhci_msm_variant_ops mci_var_ops = {
> +	.msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
> +	.msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
> +};
> +
> +static const struct sdhci_msm_variant_ops v5_var_ops = {
> +	.msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
> +	.msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
> +};
> +
> +static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
> +	.mci_removed = 0,
> +	.var_ops = &mci_var_ops,
> +	.offset = &sdhci_msm_mci_offset,
> +};
> +
> +static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
> +	.mci_removed = 1,
> +	.var_ops = &v5_var_ops,
> +	.offset = &sdhci_msm_v5_offset,
> +};
> +
>  static const struct of_device_id sdhci_msm_dt_match[] = {
>  	{ .compatible = "qcom,sdhci-msm-v4" },
>  	{},
>