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Date:   Thu, 7 Jun 2018 15:51:03 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc:     Luwei Kang <luwei.kang@...el.com>, kvm@...r.kernel.org,
        tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
        x86@...nel.org, chao.p.peng@...ux.intel.com,
        thomas.lendacky@....com, bp@...e.de, Kan.liang@...el.com,
        Janakarajan.Natarajan@....com, dwmw@...zon.co.uk,
        linux-kernel@...r.kernel.org, mathieu.poirier@...aro.org,
        kstewart@...uxfoundation.org, gregkh@...uxfoundation.org,
        pbonzini@...hat.com, rkrcmar@...hat.com, david@...hat.com,
        bsd@...hat.com, yu.c.zhang@...ux.intel.com, joro@...tes.org
Subject: Re: [PATCH v9 04/12] perf/x86/intel/pt: add new capability for Intel
 PT

On Thu, Jun 07, 2018 at 04:40:51PM +0300, Alexander Shishkin wrote:
> On Tue, May 22, 2018 at 12:52:07PM +0800, Luwei Kang wrote:
> > CPUID(EAX=14H,ECX=0):EBX[bit 3] = 1 indicates support of
> > output to Trace Transport subsystem.
> > MSR IA32_RTIT_CTL.FabricEn[bit 6] is reserved if
> > CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0.
> 
> This should instead say:
> 
> This adds support for "output to Trace Transport subsystem" capability
> of Intel PT, as documented in IA SDM Chapter 36.x.y.z. It means that
> PT can output its trace to an MMIO address range rather than system
> memory buffer.

The $subject also needs attention.

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