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Message-ID: <82D7661F83C1A047AF7DC287873BF1E167FE8E4B@SHSMSX101.ccr.corp.intel.com>
Date: Thu, 7 Jun 2018 06:50:50 +0000
From: "Kang, Luwei" <luwei.kang@...el.com>
To: "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"pbonzini@...hat.com" <pbonzini@...hat.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"peterz@...radead.org" <peterz@...radead.org>,
"alexander.shishkin@...ux.intel.com"
<alexander.shishkin@...ux.intel.com>,
"hpa@...or.com" <hpa@...or.com>
CC: "x86@...nel.org" <x86@...nel.org>,
"chao.p.peng@...ux.intel.com" <chao.p.peng@...ux.intel.com>,
"thomas.lendacky@....com" <thomas.lendacky@....com>,
"bp@...e.de" <bp@...e.de>, "Liang, Kan" <kan.liang@...el.com>,
"Janakarajan.Natarajan@....com" <Janakarajan.Natarajan@....com>,
"dwmw@...zon.co.uk" <dwmw@...zon.co.uk>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"mathieu.poirier@...aro.org" <mathieu.poirier@...aro.org>,
"kstewart@...uxfoundation.org" <kstewart@...uxfoundation.org>,
"gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
"rkrcmar@...hat.com" <rkrcmar@...hat.com>,
"david@...hat.com" <david@...hat.com>,
"bsd@...hat.com" <bsd@...hat.com>,
"yu.c.zhang@...ux.intel.com" <yu.c.zhang@...ux.intel.com>,
"joro@...tes.org" <joro@...tes.org>
Subject: RE: [PATCH v9 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit
definitions to a public header
> -----Original Message-----
> From: Kang, Luwei
> Sent: Tuesday, May 22, 2018 12:52 PM
> To: kvm@...r.kernel.org
> Cc: tglx@...utronix.de; mingo@...hat.com; hpa@...or.com; x86@...nel.org; chao.p.peng@...ux.intel.com;
> thomas.lendacky@....com; bp@...e.de; Liang, Kan <kan.liang@...el.com>; Janakarajan.Natarajan@....com;
> dwmw@...zon.co.uk; linux-kernel@...r.kernel.org; alexander.shishkin@...ux.intel.com; peterz@...radead.org;
> mathieu.poirier@...aro.org; kstewart@...uxfoundation.org; gregkh@...uxfoundation.org; pbonzini@...hat.com;
> rkrcmar@...hat.com; david@...hat.com; bsd@...hat.com; yu.c.zhang@...ux.intel.com; joro@...tes.org; Kang, Luwei
> <luwei.kang@...el.com>
> Subject: [PATCH v9 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header
>
> From: Chao Peng <chao.p.peng@...ux.intel.com>
>
> Intel Processor Trace virtualization enabling in KVM guest need to access these MSRs bit definitions, so move them to public header
> file msr-index.h.
>
> Signed-off-by: Chao Peng <chao.p.peng@...ux.intel.com>
> Signed-off-by: Luwei Kang <luwei.kang@...el.com>
> ---
> arch/x86/events/intel/pt.h | 37 -------------------------------------
> arch/x86/include/asm/msr-index.h | 33 +++++++++++++++++++++++++++++++++
> 2 files changed, 33 insertions(+), 37 deletions(-)
>
> diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h index 0eb41d0..0050ca1 100644
> --- a/arch/x86/events/intel/pt.h
> +++ b/arch/x86/events/intel/pt.h
> @@ -20,43 +20,6 @@
> #define __INTEL_PT_H__
>
> /*
> - * PT MSR bit definitions
> - */
> -#define RTIT_CTL_TRACEEN BIT(0)
> -#define RTIT_CTL_CYCLEACC BIT(1)
> -#define RTIT_CTL_OS BIT(2)
> -#define RTIT_CTL_USR BIT(3)
> -#define RTIT_CTL_PWR_EVT_EN BIT(4)
> -#define RTIT_CTL_FUP_ON_PTW BIT(5)
> -#define RTIT_CTL_CR3EN BIT(7)
> -#define RTIT_CTL_TOPA BIT(8)
> -#define RTIT_CTL_MTC_EN BIT(9)
> -#define RTIT_CTL_TSC_EN BIT(10)
> -#define RTIT_CTL_DISRETC BIT(11)
> -#define RTIT_CTL_PTW_EN BIT(12)
> -#define RTIT_CTL_BRANCH_EN BIT(13)
> -#define RTIT_CTL_MTC_RANGE_OFFSET 14
> -#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
> -#define RTIT_CTL_CYC_THRESH_OFFSET 19
> -#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
> -#define RTIT_CTL_PSB_FREQ_OFFSET 24
> -#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
> -#define RTIT_CTL_ADDR0_OFFSET 32
> -#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
> -#define RTIT_CTL_ADDR1_OFFSET 36
> -#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
> -#define RTIT_CTL_ADDR2_OFFSET 40
> -#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
> -#define RTIT_CTL_ADDR3_OFFSET 44
> -#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
> -#define RTIT_STATUS_FILTEREN BIT(0)
> -#define RTIT_STATUS_CONTEXTEN BIT(1)
> -#define RTIT_STATUS_TRIGGEREN BIT(2)
> -#define RTIT_STATUS_BUFFOVF BIT(3)
> -#define RTIT_STATUS_ERROR BIT(4)
> -#define RTIT_STATUS_STOPPED BIT(5)
> -
> -/*
> * Single-entry ToPA: when this close to region boundary, switch
> * buffers to avoid losing data.
> */
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 53d5b1b..afe4e13 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -106,7 +106,40 @@
> #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
>
> #define MSR_IA32_RTIT_CTL 0x00000570
> +#define RTIT_CTL_TRACEEN BIT(0)
> +#define RTIT_CTL_CYCLEACC BIT(1)
> +#define RTIT_CTL_OS BIT(2)
> +#define RTIT_CTL_USR BIT(3)
> +#define RTIT_CTL_PWR_EVT_EN BIT(4)
> +#define RTIT_CTL_FUP_ON_PTW BIT(5)
> +#define RTIT_CTL_CR3EN BIT(7)
> +#define RTIT_CTL_TOPA BIT(8)
> +#define RTIT_CTL_MTC_EN BIT(9)
> +#define RTIT_CTL_TSC_EN BIT(10)
> +#define RTIT_CTL_DISRETC BIT(11)
> +#define RTIT_CTL_PTW_EN BIT(12)
> +#define RTIT_CTL_BRANCH_EN BIT(13)
> +#define RTIT_CTL_MTC_RANGE_OFFSET 14
> +#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
> +#define RTIT_CTL_CYC_THRESH_OFFSET 19
> +#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
> +#define RTIT_CTL_PSB_FREQ_OFFSET 24
> +#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
> +#define RTIT_CTL_ADDR0_OFFSET 32
> +#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
> +#define RTIT_CTL_ADDR1_OFFSET 36
> +#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
> +#define RTIT_CTL_ADDR2_OFFSET 40
> +#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
> +#define RTIT_CTL_ADDR3_OFFSET 44
> +#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
> #define MSR_IA32_RTIT_STATUS 0x00000571
> +#define RTIT_STATUS_FILTEREN BIT(0)
> +#define RTIT_STATUS_CONTEXTEN BIT(1)
> +#define RTIT_STATUS_TRIGGEREN BIT(2)
> +#define RTIT_STATUS_BUFFOVF BIT(3)
> +#define RTIT_STATUS_ERROR BIT(4)
> +#define RTIT_STATUS_STOPPED BIT(5)
> #define MSR_IA32_RTIT_ADDR0_A 0x00000580
> #define MSR_IA32_RTIT_ADDR0_B 0x00000581
> #define MSR_IA32_RTIT_ADDR1_A 0x00000582
Hi,
Patch 1~5 have some code changes in x86 native for Intel Processor Trace virtualization enabling in KVM guest.
I have sent patch set v9 which include some minor changes from old version.
Do you have any comments?
Thanks,
Luwei Kang
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