linux-kernel - Re: [PATCH v5 3/4] powerpc/lib: implement strlen() in assembly

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20180608145423.GF17342@gate.crashing.org>
Date:   Fri, 8 Jun 2018 09:54:23 -0500
From:   Segher Boessenkool <segher@...nel.crashing.org>
To:     Christophe Leroy <christophe.leroy@....fr>
Cc:     Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Paul Mackerras <paulus@...ba.org>,
        Michael Ellerman <mpe@...erman.id.au>, wei.guo.simon@...il.com,
        linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 3/4] powerpc/lib: implement strlen() in assembly

Hi!

On Fri, Jun 08, 2018 at 01:27:39PM +0000, Christophe Leroy wrote:
> ---
> Not tested on PPC64.

> +#ifdef CPU_LITTLE_ENDIAN
> +	rldicl.	r8, r9, 0, 56
> +	beq	20f
> +	rldicl.	r8, r9, 56, 56
> +	beq	21f
> +	rldicl.	r8, r9, 48, 56
> +	beq	22f
> +	rldicl.	r8, r9, 40, 56
> +	beq	23f
> +	addi	r10, r10, 4
> +	rldicl.	r8, r9, 32, 56
> +	beq	20f
> +	rldicl.	r8, r9, 24, 56
> +	beq	21f
> +	rldicl.	r8, r9, 16, 56
> +	beq	22f
> +	rldicl.	r8, r9, 8, 56
> +#else
> +#ifdef CONFIG_PPC64
> +	rldicl.	r8, r9, 8, 56
> +	beq	20f
> +	rldicl.	r8, r9, 16, 56
> +	beq	21f
> +	rldicl.	r8, r9, 24, 56
> +	beq	22f
> +	rldicl.	r8, r9, 32, 56
> +	beq	23f
> +	addi	r10, r10, 4
> +#endif
> +	rlwinm.	r8, r9, 0, 0xff000000
> +	beq	20f
> +	rlwinm.	r8, r9, 0, 0x00ff0000
> +	beq	21f
> +	rlwinm.	r8, r9, 0, 0x0000ff00
> +	beq	22f
> +#endif /* CPU_LITTLE_ENDIAN */

That isn't going to perform well on processors that have more than two
or so cycles penalty on a branch mispredict (i.e. all modern processors).

ISA 2.05 and later cpus (Power6 and later) can use cmpb and a single
cntlz, on BE; on LE you can use the cnttz insn on ISA 3.0 (Power9) or
later, or do add/andc/popcntd (on ISA2.06, Power7 and later) or
neg/and/cntlz/sub.

Lots of options.  You can also write branchless code for this without
using any new insns (less nice of course).


Segher