linux-kernel - Re: [PATCH v4 24/26] irqchip/gic-v3: Add base support for pseudo-NMI

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Message-ID: <79b13ea0-a549-418c-b69f-1fad87c06357@arm.com>
Date:   Wed, 13 Jun 2018 12:14:24 +0100
From:   Julien Thierry <julien.thierry@....com>
To:     linux-arm-kernel@...ts.infradead.org
Cc:     linux-kernel@...r.kernel.org, daniel.thompson@...aro.org,
        joel@...lfernandes.org, marc.zyngier@....com, mark.rutland@....com,
        christoffer.dall@....com, james.morse@....com,
        catalin.marinas@....com, will.deacon@....com,
        Russell King <linux@...linux.org.uk>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>
Subject: Re: [PATCH v4 24/26] irqchip/gic-v3: Add base support for pseudo-NMI



On 25/05/18 10:49, Julien Thierry wrote:
> Provide a higher priority to be used for pseudo-NMIs. When such an
> interrupt is received, enter the NMI state and prevent other NMIs to
> be raised.
> 
> When returning from a pseudo-NMI, skip preemption and tracing if the
> interrupted context has interrupts disabled.
> 
> Signed-off-by: Julien Thierry <julien.thierry@....com>
> Cc: Russell King <linux@...linux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will.deacon@....com>
> Cc: Thomas Gleixner <tglx@...utronix.de>
> Cc: Jason Cooper <jason@...edaemon.net>
> Cc: Marc Zyngier <marc.zyngier@....com>
> ---
>   arch/arm/include/asm/arch_gicv3.h   |  6 ++++++
>   arch/arm64/include/asm/arch_gicv3.h |  6 ++++++
>   arch/arm64/kernel/entry.S           | 43 +++++++++++++++++++++++++++++++++++++
>   drivers/irqchip/irq-gic-v3.c        | 41 +++++++++++++++++++++++++++++++++++
>   4 files changed, 96 insertions(+)
> 

[...]

> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index b144f73..4be5996 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -371,6 +379,20 @@ static u64 gic_mpidr_to_affinity(unsigned long mpidr)
>   	return aff;
>   }
>   
> +static void do_handle_nmi(unsigned int hwirq, struct pt_regs *regs)
> +{
> +	struct pt_regs *old_regs = set_irq_regs(regs);
> +	unsigned int irq;
> +
> +	nmi_enter();

RAS/SEA also enters NMI state and things will break if asynchronous 
error occurs during a pseudo-NMI.

I'll have this fixed in the next version.

-- 
Julien Thierry