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Message-ID: <4d2482dc-a77c-6a1f-5e71-f7f14d66bf80@linux.intel.com>
Date:   Thu, 14 Jun 2018 15:05:25 +0800
From:   "Wu, Songjun" <songjun.wu@...ux.intel.com>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     hua.ma@...ux.intel.com, yixin.zhu@...ux.intel.com,
        chuanhua.lei@...el.com,
        Linux MIPS Mailing List <linux-mips@...ux-mips.org>,
        qi-ming.wu@...el.com, linux-clk@...r.kernel.org,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        James Hogan <jhogan@...nel.org>, Jiri Slaby <jslaby@...e.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Ralf Baechle <ralf@...ux-mips.org>
Subject: Re: [PATCH 4/7] tty: serial: lantiq: Always use readl()/writel()



On 6/12/2018 4:13 PM, Andy Shevchenko wrote:
> On Tue, Jun 12, 2018 at 8:40 AM, Songjun Wu <songjun.wu@...ux.intel.com> wrote:
>> Previous implementation uses platform-dependent functions
>> ltq_w32()/ltq_r32() to access registers. Those functions are not
>> available for other SoC which uses the same IP.
>> Change to OS provided readl()/writel() and readb()/writeb(), so
>> that different SoCs can use the same driver.
> This patch consists 2 or even 3 ones:
> - whitespace shuffling (indentation fixes, blank lines), I dunno if
> it's needed at all
> - some new registers / bits
> - actual switch to readl() / writel()
>
> Please, split.
It will be split to four patches, coding style, new registers, 
readl()/writel() and asc_update_bits.
>> +#define asc_w32_mask(clear, set, reg)  \
>> +       ({ typeof(reg) reg_ = (reg);    \
>> +       writel((readl(reg_) & ~(clear)) | (set), reg_); })
> This would be better as a static inline helper, and name is completely
> misleading, it doesn't mask the register bits, it _updates_ them.
It will be changed to asc_update_bits.

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