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Message-ID: <CAK8P3a0K6qezHLcjkeq0zd+iQJQc_qbT2JhtZGrCNRT495sUvQ@mail.gmail.com>
Date: Thu, 14 Jun 2018 12:07:19 +0200
From: Arnd Bergmann <arnd@...db.de>
To: Songjun Wu <songjun.wu@...ux.intel.com>
Cc: hua.ma@...ux.intel.com, yixin.zhu@...ux.intel.com,
chuanhua.lei@...el.com,
"open list:RALINK MIPS ARCHITECTURE" <linux-mips@...ux-mips.org>,
qi-ming.wu@...el.com, linux-clk <linux-clk@...r.kernel.org>,
linux-serial@...r.kernel.org, DTML <devicetree@...r.kernel.org>,
James Hogan <jhogan@...nel.org>, Jiri Slaby <jslaby@...e.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Ralf Baechle <ralf@...ux-mips.org>
Subject: Re: [PATCH 4/7] tty: serial: lantiq: Always use readl()/writel()
On Tue, Jun 12, 2018 at 7:40 AM, Songjun Wu <songjun.wu@...ux.intel.com> wrote:
> Previous implementation uses platform-dependent functions
> ltq_w32()/ltq_r32() to access registers. Those functions are not
> available for other SoC which uses the same IP.
> Change to OS provided readl()/writel() and readb()/writeb(), so
> that different SoCs can use the same driver.
>
> Signed-off-by: Songjun Wu <songjun.wu@...ux.intel.com>
Are there any big-endian machines using this driver? The original definition
of ltq_r32() uses non-byteswapping __raw_readl() etc, which suggests
that the registers might be wired up in a way that matches the CPU
endianess (this is usally a bad idea in hardware design, but nothing
we can influence in the OS).
When you change it to readl(), that will breaks all machines that rely
on the old behavior on big-endian kernels.
Arnd
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