linux-kernel - [PATCH v5 3/3] ARM: dts: Renesas R9A06G032 SMP enable method

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Message-Id: <1528973943-28132-4-git-send-email-michel.pollet@bp.renesas.com>
Date:   Thu, 14 Jun 2018 11:58:58 +0100
From:   Michel Pollet <michel.pollet@...renesas.com>
To:     linux-renesas-soc@...r.kernel.org,
        Simon Horman <horms@...ge.net.au>
Cc:     phil.edworthy@...esas.com,
        Michel Pollet <buserror+upstream@...il.com>,
        Michel Pollet <michel.pollet@...renesas.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Magnus Damm <magnus.damm@...il.com>,
        Russell King <linux@...linux.org.uk>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Frank Rowand <frank.rowand@...y.com>,
        Maxime Ripard <maxime.ripard@...tlin.com>,
        Carlo Caione <carlo@...lessm.com>,
        Stefan Wahren <stefan.wahren@...e.com>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Andreas Färber <afaerber@...e.de>,
        Florian Fainelli <f.fainelli@...il.com>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v5 3/3] ARM: dts: Renesas R9A06G032 SMP enable method

Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.

Signed-off-by: Michel Pollet <michel.pollet@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 353e06f..3e45375 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -30,6 +30,8 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+			enable-method = "renesas,r9a06g032-smp";
+			cpu-release-addr = <0 0x4000c204>;
 		};
 	};
 
-- 
2.7.4