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Message-ID: <SN1PR02MB3758971F60A9800642B16F95B87D0@SN1PR02MB3758.namprd02.prod.outlook.com>
Date: Thu, 14 Jun 2018 18:30:03 +0000
From: Jolly Shah <JOLLYS@...inx.com>
To: Randy Dunlap <rdunlap@...radead.org>,
"ard.biesheuvel@...aro.org" <ard.biesheuvel@...aro.org>,
"mingo@...nel.org" <mingo@...nel.org>,
"gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
"matt@...eblueprint.co.uk" <matt@...eblueprint.co.uk>,
"sudeep.holla@....com" <sudeep.holla@....com>,
"hkallweit1@...il.com" <hkallweit1@...il.com>,
"keescook@...omium.org" <keescook@...omium.org>,
"dmitry.torokhov@...il.com" <dmitry.torokhov@...il.com>,
"mturquette@...libre.com" <mturquette@...libre.com>,
"sboyd@...eaurora.org" <sboyd@...eaurora.org>,
"michal.simek@...inx.com" <michal.simek@...inx.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
CC: Rajan Vaja <RAJANV@...inx.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
Tejas Patel <TEJASP@...inx.com>,
Shubhrajyoti Datta <shubhraj@...inx.com>
Subject: RE: [PATCH v7 10/10] drivers: clk: Add ZynqMP clock driver
Hi Randy,
Thanks for review,
> -----Original Message-----
> From: Randy Dunlap [mailto:rdunlap@...radead.org]
> Sent: Wednesday, May 30, 2018 2:18 PM
> To: Jolly Shah <JOLLYS@...inx.com>; ard.biesheuvel@...aro.org;
> mingo@...nel.org; gregkh@...uxfoundation.org; matt@...eblueprint.co.uk;
> sudeep.holla@....com; hkallweit1@...il.com; keescook@...omium.org;
> dmitry.torokhov@...il.com; mturquette@...libre.com;
> sboyd@...eaurora.org; michal.simek@...inx.com; robh+dt@...nel.org;
> mark.rutland@....com; linux-clk@...r.kernel.org
> Cc: Rajan Vaja <RAJANV@...inx.com>; linux-arm-kernel@...ts.infradead.org;
> linux-kernel@...r.kernel.org; devicetree@...r.kernel.org; Tejas Patel
> <TEJASP@...inx.com>; Shubhrajyoti Datta <shubhraj@...inx.com>; Jolly Shah
> <JOLLYS@...inx.com>
> Subject: Re: [PATCH v7 10/10] drivers: clk: Add ZynqMP clock driver
>
> On 05/30/2018 01:55 PM, Jolly Shah wrote:
> > From: Jolly Shah <jolly.shah@...inx.com>
>
>
> > diff --git a/drivers/clk/zynqmp/Kconfig b/drivers/clk/zynqmp/Kconfig
> > new file mode 100644 index 0000000..fe815f7
> > --- /dev/null
> > +++ b/drivers/clk/zynqmp/Kconfig
> > @@ -0,0 +1,11 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +config COMMON_CLK_ZYNQMP
> > + bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
> > + depends on OF
> > + depends on ARCH_ZYNQMP || COMPILE_TEST
> > + depends on ZYNQMP_FIRMWARE
> > + help
> > + Support for the Zynqmp Ultrascale clock controller.
> > + It has a dependency on the PMU firmware.
> > + Say Y if you want to support clock support
>
> Say Y if you want to include clock support.
>
Fixed in v8
>
> --
> ~Randy
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