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Message-ID: <CAHLCerOBTbBGC61qD=u1=4GWi=w64rPbWXFFGdv-9B-UO8A5BQ@mail.gmail.com>
Date:   Fri, 15 Jun 2018 16:07:20 +0300
From:   Amit Kucheria <amit.kucheria@...durent.com>
To:     Taniya Das <tdas@...eaurora.org>
Cc:     "Rafael J. Wysocki" <rjw@...ysocki.net>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Linux PM list <linux-pm@...r.kernel.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>, Rob Herring <robh@...nel.org>,
        Saravana Kannan <skannan@...eaurora.org>
Subject: Re: [PATCH v4 1/2] dt-bindings: cpufreq: Introduce QCOM CPUFREQ FW bindings

On Tue, Jun 12, 2018 at 2:02 PM, Taniya Das <tdas@...eaurora.org> wrote:
> Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
> SoCs. This is required for managing the cpu frequency transitions which are
> controlled by firmware.
>
> Signed-off-by: Taniya Das <tdas@...eaurora.org>


> +       qcom,cpufreq-fw {
> +               compatible = "qcom,cpufreq-fw";
> +
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +
> +               freq_domain_table0 : freq_table0 {
> +                       reg = <0x17d43920 0x4>, <0x17d43110 0x500>,
> +                                <0x17d41000 0x4>;

Changing the enable address to 0x17d43000 would make this a working
example, I think.

> +                       reg-names = "perf", "lut", "enable";
> +               };
> +
> +               freq_domain_table1 : freq_table1 {
> +                       reg = <0x17d46120 0x4>, <0x17d45910 0x500>,
> +                               <0x17d45800 0x4> ;
> +                       reg-names = "perf", "lut", "enable";
> +               };
> +       };

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