linux-kernel - Re: [RFC PATCH 5/6] arm64: dts: ti: Add Support for AM654 SoC

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Message-ID: <a69fcb7a-f7a1-481b-8a02-1da7d1e20671@ti.com>
Date:   Fri, 15 Jun 2018 19:08:14 +0530
From:   Sekhar Nori <nsekhar@...com>
To:     Tony Lindgren <tony@...mide.com>, Nishanth Menon <nm@...com>
CC:     Mark Rutland <mark.rutland@....com>, <devicetree@...r.kernel.org>,
        Sudeep Holla <sudeep.holla@....com>,
        Vignesh R <vigneshr@...com>,
        Catalin Marinas <catalin.marinas@....com>,
        Santosh Shilimkar <ssantosh@...nel.org>,
        Will Deacon <will.deacon@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Russell King <linux@...linux.org.uk>,
        Tero Kristo <t-kristo@...com>,
        Rob Herring <robh+dt@...nel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [RFC PATCH 5/6] arm64: dts: ti: Add Support for AM654 SoC

Hi Tony,

On Friday 15 June 2018 10:31 AM, Tony Lindgren wrote:
> * Nishanth Menon <nm@...com> [180614 13:07]:
>> On 12:38-20180614, Tony Lindgren wrote:

>> From A53 view, a more accurate view might be  - from an interconnect
>> view of the world (still simplified - i have ignored the sub bus
>> segments in the representations below):
>>
>> msmc {
>> 	navss_main {
>> 		cbass_main{
>> 			cbass_mcu {
>> 				navss_mcu {
>> 				};
>> 				cbass_wkup{
>> 				};
>> 			};
>> 		};
>> 	};
>> };
>>
>> From R5 view, the view will be very different ofcourse:
>> view of the world (still simplified):
>>
>> cbass_mcu {
>> 	navss_mcu {
>> 	};
>> 	cbass_wkup{
>> 	};
>> 	cbass_main{
>> 		navss_main {
>> 			msmc {
>> 			};
>> 		};
>> 	};
>> };
> 
> Well if we follow the hardware representation of the interconnects,
> it should not matter from which processor view you're looking at things.
> There are just different ranges provided.

AFAIK, the root node needs to have the CPU which is using the DT. So,
the hierarchy will change based on CPU view (if we describe it fully).

How well we can reuse individual interconnect segments is something I
have to think about / experiment. Will have to be wary of any "short
paths" or "cross connections".

Thanks,
Sekhar