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Message-ID: <eaf86ae1-75f3-b49c-781c-33ebac532eb2@linux.intel.com>
Date:   Mon, 18 Jun 2018 09:16:19 -0700
From:   Dave Hansen <dave.hansen@...ux.intel.com>
To:     Keno Fischer <keno@...iacomputing.com>
Cc:     Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, x86@...nel.org,
        "H. Peter Anvin" <hpa@...or.com>, Borislav Petkov <bp@...e.de>,
        Andi Kleen <andi@...stfloor.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Kyle Huey <khuey@...ehuey.com>,
        Robert O'Callahan <robert@...llahan.org>
Subject: Re: [RFC PATCH] x86/arch_prctl: Add ARCH_SET_XCR0 to mask XCR0
 per-thread

On 06/18/2018 08:13 AM, Keno Fischer wrote:
>>> 4) Catch the fault thrown by xsaves/xrestors in this situation, update
>>>     XCR0, redo the xsaves/restores, put XCR0 back and continue
>>>     execution after the faulting instruction.
>>
>> I'm worried about the kernel pieces that go digging in the XSAVE data
>> getting confused more than the hardware getting confused.
> 
> So you prefer this option? If so, I can try to have a go at implementing it
> this way and seeing if I run into any trouble.

No, I'm saying that depending on faults is not a viable solution.  We
are not guaranteed to get faults in all the cases you would need to fix up.

XSAVE*/XRSTOR* are not even *called* in some of those cases.

>>> At least currently, it is my understanding that `xfeatures_mask` only has
>>> user features, am I mistaken about that?
>>
>> We're slowing adding supervisor support.  I think accounting for
>> supervisor features is a requirement for any new XSAVE code.
> 
> Sure, I don't think this is in any way incompatible with that (though
> probably also informs that we want to keep the memory layout the
> same if possible).

I think you've tried to simplify your implementation by ignoring
features, like holes.  However, the existing implementation actually
*does* handle those things and we've spent a significant amount of time
ensuring that it works, despite the fact that you can't buy an
off-the-shelf CPU that creates a hole without help from a hypervisor today.

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