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Message-ID: <1529397769.26480.16.camel@mtksdaap41>
Date: Tue, 19 Jun 2018 16:42:49 +0800
From: CK Hu <ck.hu@...iatek.com>
To: Stu Hsieh <stu.hsieh@...iatek.com>
CC: Philipp Zabel <p.zabel@...gutronix.de>,
David Airlie <airlied@...ux.ie>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
<dri-devel@...ts.freedesktop.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>, <srv_heupstream@...iatek.com>
Subject: Re: [PATCH v6 20/29] drm/mediatek: add connection from RDMA2 to DPI0
On Tue, 2018-06-19 at 15:34 +0800, Stu Hsieh wrote:
> This patch add the connection from RDMA2 to DPI0
>
Reviewed-by: CK Hu <ck.hu@...iatek.com>
> Signed-off-by: Stu Hsieh <stu.hsieh@...iatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index d0d5f337ce14..c88742a6c2b9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -31,6 +31,7 @@
> #define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> @@ -91,7 +92,9 @@
> #define RDMA1_SOUT_DSI1 0x1
> #define RDMA1_SOUT_DSI2 0x4
> #define RDMA1_SOUT_DSI3 0x5
> +#define RDMA2_SOUT_DPI0 0x2
> #define DPI0_SEL_IN_RDMA1 0x1
> +#define DPI0_SEL_IN_RDMA2 0x3
> #define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> #define DSI1_SEL_IN_RDMA1 0x1
> #define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> @@ -193,6 +196,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> value = RDMA1_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI0;
> } else {
> value = 0;
> }
> @@ -224,6 +230,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> value = DSI3_SEL_IN_RDMA1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> + value = DPI0_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> value = COLOR1_SEL_IN_OVL1;
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