lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <e15ea4689014ff69eed0c0b93552c4da@codeaurora.org>
Date:   Fri, 22 Jun 2018 11:39:50 +0530
From:   Abhishek Sahu <absahu@...eaurora.org>
To:     Sricharan R <sricharan@...eaurora.org>
Cc:     andy.gross@...aro.org, david.brown@...aro.org, robh+dt@...nel.org,
        mark.rutland@....com, linux-arm-msm@...r.kernel.org,
        linux-soc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-msm-owner@...r.kernel.org
Subject: Re: [PATCH] arm: dts: qcom: Fix 'interrupts = <>' property to use
 proper  macros

On 2018-06-20 14:53, Sricharan R wrote:
> Fix all nodes to use proper GIC_* macros for the interrupt type and the
> interrupt trigger settings to avoid the boot warnings.

  Thanks Sricharan for fixing these warnings.

  Applied over 4.18 rc1 and tested in IPQ8064 AP148 board.
  No backtraces are coming during boottime and IRQ seems OK.

  root@...nWrt:/# cat /proc/interrupts
            CPU0       CPU1
  16:       2602       4750     GIC-0  18 Edge      gp_timer
  17:          0          0     GIC-0  26 Level     arm-pmu
  23:         19          0     GIC-0 241 Level     ahci[29000000.sata]
  24:        912          0     GIC-0 184 Level     msm_serial0
  25:        113          0     GIC-0 185 Level     i2c_qup
  26:          6          0     GIC-0 187 Level     1a280000.spi
IPI0:          0          0  CPU wakeup interrupts
IPI1:          0          0  Timer broadcast interrupts
IPI2:       2045       1713  Rescheduling interrupts
IPI3:          1          4  Function call interrupts
IPI4:          0          0  CPU stop interrupts
IPI5:          0          0  IRQ work interrupts
IPI6:          0          0  completion interrupts
Err:          0

> 
> Signed-off-by: Sricharan R <sricharan@...eaurora.org>

Tested-by: Abhishek Sahu <absahu@...eaurora.org>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ