linux-kernel - Re: [PATCH 2/2] tools/memory-model: Add write ordering by release-acquire and by locks

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Message-ID: <20180622112553.GA10658@andrea>
Date:   Fri, 22 Jun 2018 13:25:53 +0200
From:   Andrea Parri <andrea.parri@...rulasolutions.com>
To:     Will Deacon <will.deacon@....com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Alan Stern <stern@...land.harvard.edu>,
        LKMM Maintainers -- Akira Yokosawa <akiyks@...il.com>,
        Boqun Feng <boqun.feng@...il.com>,
        David Howells <dhowells@...hat.com>,
        Jade Alglave <j.alglave@....ac.uk>,
        Luc Maranget <luc.maranget@...ia.fr>,
        Nicholas Piggin <npiggin@...il.com>,
        "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
        Kernel development list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] tools/memory-model: Add write ordering by
 release-acquire and by locks

> > > I also just realised that this prevents Power from using ctrl+isync to
> > > implement acquire, should they wish to do so.
> > 
> > They in fact do so on chips lacking LWSYNC, see how PPC_ACQUIRE_BARRIER
> > (as used by atomic_*_acquire) turns into ISYNC (note however that they
> > do not use PPC_ACQUIRE_BARRIER for smp_load_acquire -- because there's
> > no CTRL there).
> 
> Right, so the example in the commit message is broken on PPC then. I think
> it's also broken on RISC-V, despite the claim.

I agree for RISC-V (and I missed it in my earlier review): the 2nd
snippet from the commit message would map to something like

   fence rw, w
   STORE #1,[x]
   LOAD  [x]
   fence r ,rw
   STORE #1,[y]

and there would be no guarantee that the stores to x and y will be
propagated in program order to another CPU, AFAICT.  Thank you for
pointing this out.

  Andrea