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Date: Wed, 27 Jun 2018 11:07:57 +0000
From: Naga Sureshkumar Relli <nagasure@...inx.com>
To: Naga Sureshkumar Relli <nagasure@...inx.com>,
Boris Brezillon <boris.brezillon@...tlin.com>
CC: "richard@....at" <richard@....at>,
"dwmw2@...radead.org" <dwmw2@...radead.org>,
"computersforpeace@...il.com" <computersforpeace@...il.com>,
"marek.vasut@...il.com" <marek.vasut@...il.com>,
"f.fainelli@...il.com" <f.fainelli@...il.com>,
"mmayer@...adcom.com" <mmayer@...adcom.com>,
"rogerq@...com" <rogerq@...com>,
"ladis@...ux-mips.org" <ladis@...ux-mips.org>,
"ada@...rsis.com" <ada@...rsis.com>,
"honghui.zhang@...iatek.com" <honghui.zhang@...iatek.com>,
"miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
"nagasureshkumarrelli@...il.com" <nagasureshkumarrelli@...il.com>,
Michal Simek <michals@...inx.com>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [[LINUX PATCH v10] 1/4] Devicetree: Add pl353 smc controller
devicetree binding information
Hi Boris,
> -----Original Message-----
> From: Naga Sureshkumar Relli [mailto:nagasure@...inx.com]
> Sent: Monday, June 25, 2018 2:30 PM
> To: Boris Brezillon <boris.brezillon@...tlin.com>
> Cc: richard@....at; dwmw2@...radead.org; computersforpeace@...il.com;
> marek.vasut@...il.com; f.fainelli@...il.com; mmayer@...adcom.com; rogerq@...com;
> ladis@...ux-mips.org; ada@...rsis.com; honghui.zhang@...iatek.com;
> miquel.raynal@...tlin.com; nagasureshkumarrelli@...il.com; Michal Simek
> <michals@...inx.com>; linux-mtd@...ts.infradead.org; linux-kernel@...r.kernel.org
> Subject: RE: [[LINUX PATCH v10] 1/4] Devicetree: Add pl353 smc controller devicetree
> binding information
>
> Hi Boris,
>
>
> > -----Original Message-----
> > From: Boris Brezillon [mailto:boris.brezillon@...tlin.com]
> > Sent: Monday, June 25, 2018 2:10 AM
> > To: Naga Sureshkumar Relli <nagasure@...inx.com>
> > Cc: richard@....at; dwmw2@...radead.org; computersforpeace@...il.com;
> > marek.vasut@...il.com; f.fainelli@...il.com; mmayer@...adcom.com;
> > rogerq@...com; ladis@...ux-mips.org; ada@...rsis.com;
> > honghui.zhang@...iatek.com; miquel.raynal@...tlin.com;
> > nagasureshkumarrelli@...il.com; Michal Simek <michals@...inx.com>;
> > linux-mtd@...ts.infradead.org; linux-kernel@...r.kernel.org
> > Subject: Re: [[LINUX PATCH v10] 1/4] Devicetree: Add pl353 smc
> > controller devicetree binding information
> >
> > Hi Naga,
> >
> > Subject prefix should be "dt-bindings: memory: " not "Devicetree: ".
> Ok, I will change it.
>
> >
> > On Thu, 21 Jun 2018 12:12:28 +0530
> > Naga Sureshkumar Relli <naga.sureshkumar.relli@...inx.com> wrote:
> >
> > > Add pl353 static memory controller devicetree binding information.
> > >
> > > Signed-off-by: Naga Sureshkumar Relli
> > > <naga.sureshkumar.relli@...inx.com>
> > > ---
> > > Changes in v10:
> > > - Corrected the typos like "should be" to "Must be" and nand to NAND etc..
> > > - Removed padding to describe size-cells and address-cells
> > > - Removed timing parameters from DT, and added ->setup_data_interface() hook
> > > to the driver to read the SDR timings
> > > - Modified label name from "pl353smcc_0: pl353smcc@...0e000" to
> > > "smcc: memory-controller@...0e000" as suggested by Miquel Changes
> > > in v9:
> > > - Addressed below comments given by Randy Dunlap and Miquel Raynal
> > > - Typos
> > > - Added extra documentation that explains the HW ECC limitation with SMC
> > > (Comments given to v8: https://lkml.org/lkml/2018/3/22/23)
> > > Changes in v8:
> > > - None
> > > Changes in v7:
> > > - Corrected clocks description
> > > - prefixed '#' for address and size cells Changes in v6:
> > > - None
> > > Changes in v5:
> > > - Removed timing properties
> > > Changes in v4:
> > > - none
> > > Changes in v3:
> > > - none
> > > Changes in v2:
> > > - modified timing binding info as per onfi timing parameters
> > > - add suffix nano second as timing unit
> > > - modified the clock names as per the IP spec
> > > ---
> > > .../bindings/memory-controllers/pl353-smc.txt | 41
> > ++++++++++++++++++++++
> > > 1 file changed, 41 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > > b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > > new file mode 100644
> > > index 0000000..8b4c65e
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc
> > > +++ .t
> > > +++ xt
> > > @@ -0,0 +1,41 @@
> > > +Device tree bindings for ARM PL353 static memory controller
> > > +
> > > +PL353 static memory controller supports two kinds of memory
> > > +interfaces.i.e NAND and SRAM/NOR interfaces.
> > > +The actual devices are instantiated from the child nodes of pl353 smc node.
> > > +
> > > +Required properties:
> > > +- compatible : Must be "arm,pl353-smc-r2p1"
> > > +- reg : Controller registers map and length.
> > > +- clock-names : List of input clock names - "ref_clk", "aper_clk"
> > > + (See clock bindings for details).
> > > +- clocks : Clock phandles (see clock bindings for details).
> > > +- address-cells : Must be 1.
> > > +- size-cells : Must be 1.
> > > +
> > > +Child nodes:
> > > + For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash"
> > > +drivers are supported as child nodes.
> > > +
> > > +for NAND partition information please refer the below file
> > > +Documentation/devicetree/bindings/mtd/partition.txt
> > > +
> > > +Example:
> > > + smcc: memory-controller@...0e000
> > > + compatible = "arm,pl353-smc-r2p1"
> > > + clock-names = "memclk", "aclk";
> > > + clocks = <&clkc 11>, <&clkc 44>;
> > > + reg = <0xe000e000 0x1000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > > + nand_0: flash@...00000 {
> > > + compatible = "arm,pl353-nand-r2p1"
> > > + reg = <0xe1000000 0x1000000>;
> > > + (...)
> > > + };
> > > + nor0: flash@...00000 {
> > > + compatible = "cfi-flash";
> > > + reg = <0xe2000000 0x2000000>;
> > > + };
> > > + };
> >
> > I had a look at the PL353 TRM, and the block diagram looks very
> > similar to the atmel EBI/SMC one. AHB/AXI memory ranges that are used
> > to interact with the memories are assigned CS ids, which can then be
> > used to configure the timings (and other kind of stuff). I think you
> > should have #address-cells = <2>, the first cell encoding the CS id, and the second one, the
> memory offset within the reserved range for this CS id.
> > See the atmel,ebi binding [1].
> >
> To my previous patch, as per your comments, I modified reading timing parameters from dts
> To nand_setup_data_interface() hook, But I didn't see the CS implementation as per atmel EBI
> driver.
> Sure, I will update like that and will send v11.
I have seen the atmel-ebi driver, it is doing more compare to PL353.
It works with
drivers/mfd/
drivers/mtd/
drivers/memory/
but if we compare that with PL353 SMC, then
In nand case, we have only one CS and for NOR/SRAM we have 2 CS.
i.e
PL353 SMC -> NAND (1CS)
NOR/SRAM(2CS).
So just asking, will there be any advantage if we do like that?
Because, for NOR/SRAM interface, the generic cfi-probe will take care and
For NAND, PL353 has just one NAND, hence asking.
Could you please explain a bit more?
Thanks,
Naga Sureshkumar Relli
>
> Thanks,
> Naga Sureshkumar Relli
>
> > Regards,
> >
> > Boris
> >
> > [1]https://elixir.bootlin.com/linux/v4.18-
> > rc2/source/Documentation/devicetree/bindings/memory-controllers/atmel,
> > ebi.txt
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