linux-kernel - Re: [PATCH v2 1/2] clk: pxa: export 32kHz PLL

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Message-ID: <201806270855.xvEN3vnK%fengguang.wu@intel.com>
Date:   Wed, 27 Jun 2018 08:16:16 +0800
From:   kbuild test robot <lkp@...el.com>
To:     Robert Jarzmik <robert.jarzmik@...e.fr>
Cc:     kbuild-all@...org, Daniel Mack <daniel@...que.org>,
        Haojian Zhuang <haojian.zhuang@...il.com>,
        Robert Jarzmik <robert.jarzmik@...e.fr>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 1/2] clk: pxa: export 32kHz PLL

Hi Robert,

I love your patch! Yet something to improve:

[auto build test ERROR on clk/clk-next]
[also build test ERROR on v4.18-rc2 next-20180626]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Robert-Jarzmik/clk-pxa-export-32kHz-PLL/20180627-040726
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-xcep_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   drivers/clk/pxa/clk-pxa25x.c: In function 'pxa25x_register_plls':
>> drivers/clk/pxa/clk-pxa25x.c:298:17: error: expected ')' before ';' token
              32768);
                    ^
>> drivers/clk/pxa/clk-pxa25x.c:304:1: error: expected ';' before '}' token
    }
    ^

vim +298 drivers/clk/pxa/clk-pxa25x.c

   290	
   291	static void __init pxa25x_register_plls(void)
   292	{
   293		clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
   294					CLK_GET_RATE_NOCACHE, 3686400);
   295		clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
   296				    clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
   297							    CLK_GET_RATE_NOCACHE,
 > 298							    32768);
   299		clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
   300		clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
   301					  0, 26, 1);
   302		clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
   303					  0, 40, 1);
 > 304	}
   305	

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