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Date:   Wed, 27 Jun 2018 18:19:57 -0700
From:   Chris Lew <clew@...eaurora.org>
To:     bjorn.andersson@...aro.org, andy.gross@...aro.org,
        david.brown@...aro.org
Cc:     aneela@...eaurora.org, linux-arm-msm@...r.kernel.org,
        linux-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
        clew@...eaurora.org
Subject: [PATCH] rpmsg: glink: Set tail pointer to 0 at end of FIFO

When wrapping around the FIFO, the remote expects the tail pointer to
be reset to 0 on the edge case where the tail equals the FIFO length.

Signed-off-by: Chris Lew <clew@...eaurora.org>
---
 drivers/rpmsg/qcom_glink_smem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/rpmsg/qcom_glink_smem.c b/drivers/rpmsg/qcom_glink_smem.c
index 2b5cf2790954..7a276be598d6 100644
--- a/drivers/rpmsg/qcom_glink_smem.c
+++ b/drivers/rpmsg/qcom_glink_smem.c
@@ -109,7 +109,7 @@ static void glink_smem_rx_advance(struct qcom_glink_pipe *np,
 	tail = le32_to_cpu(*pipe->tail);
 
 	tail += count;
-	if (tail > pipe->native.length)
+	if (tail >= pipe->native.length)
 		tail -= pipe->native.length;
 
 	*pipe->tail = cpu_to_le32(tail);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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