linux-kernel - Re: [PATCH v7 3/3] ARM: dts: Renesas R9A06G032 SMP enable method

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Thu, 28 Jun 2018 14:18:14 +0200
From:   Simon Horman <horms@...ge.net.au>
To:     Michel Pollet <michel.pollet@...renesas.com>
Cc:     linux-renesas-soc@...r.kernel.org, phil.edworthy@...esas.com,
        Michel Pollet <buserror+upstream@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Magnus Damm <magnus.damm@...il.com>,
        Douglas Anderson <dianders@...omium.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Stefan Wahren <stefan.wahren@...e.com>,
        Carlo Caione <carlo@...lessm.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v7 3/3] ARM: dts: Renesas R9A06G032 SMP enable method

On Thu, Jun 28, 2018 at 09:17:14AM +0100, Michel Pollet wrote:
> Add a special enable method for the second CA7 of the R9A06G032
> as well as the default value for the "cpu-release-addr" property.
> 
> Signed-off-by: Michel Pollet <michel.pollet@...renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>

Thanks, applied.

I had to manually resolve a conflict due to updates to the patch
that added this dtsi file (as noted elsewhere). Please check that this is
correct.


From: Michel Pollet <michel.pollet@...renesas.com>
Subject: [PATCH] ARM: dts: Renesas R9A06G032 SMP enable method

Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.

Signed-off-by: Michel Pollet <michel.pollet@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 339d0958011e..afe29c95a006 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -29,6 +29,8 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clocks = <&sysctrl 84>;
+			enable-method = "renesas,r9a06g032-smp";
+			cpu-release-addr = <0 0x4000c204>;
 		};
 	};
 
-- 
2.11.0