[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3131254.YlICBQirlu@jernej-laptop>
Date: Fri, 29 Jun 2018 21:19:33 +0200
From: Jernej Škrabec <jernej.skrabec@...l.net>
To: Chen-Yu Tsai <wens@...e.org>
Cc: Maxime Ripard <maxime.ripard@...tlin.com>,
Rob Herring <robh+dt@...nel.org>,
David Airlie <airlied@...ux.ie>,
Gustavo Padovan <gustavo@...ovan.org>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Sean Paul <seanpaul@...omium.org>,
Mark Rutland <mark.rutland@....com>,
dri-devel <dri-devel@...ts.freedesktop.org>,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-clk <linux-clk@...r.kernel.org>,
linux-sunxi <linux-sunxi@...glegroups.com>
Subject: Re: [PATCH v3 16/24] drm/sun4i: Enable DW HDMI PHY clock
Dne četrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec <jernej.skrabec@...l.net>
wrote:
> > Current DW HDMI PHY code never prepares and enables PHY clock after it is
> > created. It's just used as it is. This may work in some cases, but it's
> > clearly wrong. Fix it by adding proper calls to enable/disable PHY
> > clock.
> >
> > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant")
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@...l.net>
>
> So why does it work on the H3? Because there's only one PLL that the whole
> display pipeline uses?
>
> We should probably tag this for stable. So,
>
> Cc: <stable@...r.kernel.org>
> Reviewed-by: Chen-Yu Tsai <wens@...e.org>
Same question as before, how this should be handled? Can I send separate patch
with same content to stable ML only?
Best regards,
Jernej
Powered by blists - more mailing lists