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Message-ID: <20180702205146.GA129942@google.com>
Date: Mon, 2 Jul 2018 13:51:46 -0700
From: Matthias Kaehlcke <mka@...omium.org>
To: Doug Anderson <dianders@...omium.org>
Cc: Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
"open list:ARM/QUALCOMM SUPPORT" <linux-soc@...r.kernel.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
LKML <linux-kernel@...r.kernel.org>,
David Collins <collinsd@...eaurora.org>,
Stephen Boyd <sboyd@...nel.org>
Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: pm8998: Add spmi-temp-alarm node
On Mon, Jul 02, 2018 at 01:12:01PM -0700, Doug Anderson wrote:
> Hi,
>
> On Mon, Jul 2, 2018 at 11:10 AM, Matthias Kaehlcke <mka@...omium.org> wrote:
> > This adds the spmi-temp-alarm node to pm8998 based on the examples in the
> > bindings.
> >
> > Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
> > ---
> > Changes in v2:
> > - none
> >
> > arch/arm64/boot/dts/qcom/pm8998.dtsi | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi
> > index 92bed1e7d4bb..2f4989e7ef68 100644
> > --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
> > @@ -11,6 +11,13 @@
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > + pm8998_temp: qcom,temp-alarm@...0 {
>
> Remove "qcom," from the node name (AKA please change to
> "temp-alarm@...0"). Someone internal in Qualcomm seems to have
> started this trend so you see it on all downstream kernels, but
> upstream device tree isn't supposed to have it.
Ok, thanks
> > + compatible = "qcom,spmi-temp-alarm";
> > + reg = <0x2400 0x100>;
>
> Why are there two numbers for the "reg"? Should just be 0x2400.
>From /Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt:
Required properties:
...
- reg: Specifies the SPMI address and length of the controller's
registers.
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