linux-kernel - Re: [PATCH 2/2] x86/bugs: Fix the AMD SSBD usage of the SPEC

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Message-ID: <20180703141212.GK8404@char.us.oracle.com>
Date:   Tue, 3 Jul 2018 10:12:12 -0400
From:   Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>
To:     Tom Lendacky <thomas.lendacky@....com>
Cc:     x86@...nel.org, linux-kernel@...r.kernel.org,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Borislav Petkov <bpetkov@...e.de>,
        David Woodhouse <dwmw@...zon.co.uk>
Subject: Re: [PATCH 2/2] x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR

On Mon, Jul 02, 2018 at 04:36:02PM -0500, Tom Lendacky wrote:
> On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the
> SSBD mitigation support should use the SPEC_CTRL MSR. Other features could
> have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD
> mitigation option is in place.
> 
> Update the SSBD support to check for the actual SSBD features that will
> use the SPEC_CTRL MSR.
> 
> Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage")
> Signed-off-by: Tom Lendacky <thomas.lendacky@....com>

Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>

Thank you!
> ---
>  arch/x86/kernel/cpu/bugs.c |    8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
> index 404df26..5c0ea39 100644
> --- a/arch/x86/kernel/cpu/bugs.c
> +++ b/arch/x86/kernel/cpu/bugs.c
> @@ -155,7 +155,8 @@ enum spectre_v2_mitigation_cmd {
>  		guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
>  
>  		/* SSBD controlled in MSR_SPEC_CTRL */
> -		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
> +		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
> +		    static_cpu_has(X86_FEATURE_AMD_SSBD))
>  			hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
>  
>  		if (hostval != guestval) {
> @@ -533,9 +534,10 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
>  		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
>  		 * use a completely different MSR and bit dependent on family.
>  		 */
> -		if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
> +		if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
> +		    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
>  			x86_amd_ssb_disable();
> -		else {
> +		} else {
>  			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
>  			x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
>  			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
>