linux-kernel - Re: [PATCH 3/3] clk: meson: add sub EMMC clock controller driver

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Message-ID: <1530691628.2900.216.camel@baylibre.com>
Date:   Wed, 04 Jul 2018 10:07:08 +0200
From:   Jerome Brunet <jbrunet@...libre.com>
To:     Yixun Lan <yixun.lan@...ogic.com>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc:     robh@...nel.org, Neil Armstrong <narmstrong@...libre.com>,
        sboyd@...nel.org, khilman@...libre.com, mturquette@...libre.com,
        linux-kernel@...r.kernel.org, boris.brezillon@...tlin.com,
        jian.hu@...ogic.com, liang.yang@...ogic.com,
        qiufang.dai@...ogic.com, miquel.raynal@...tlin.com,
        carlo@...one.org, linux-amlogic@...ts.infradead.org,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 3/3] clk: meson: add sub EMMC clock controller driver

On Wed, 2018-07-04 at 15:17 +0800, Yixun Lan wrote:
> > you are describing the mux and the divider here
> > however, meson-gx-mmc.c has a few more clock related bits:
> > - CLK_CORE_PHASE_MASK
> > - CLK_TX_PHASE_MASK
> > - CLK_RX_PHASE_MASK
> > - CLK_V2_TX_DELAY_MASK / CLK_V3_TX_DELAY_MASK
> > - CLK_V2_RX_DELAY_MASK / CLK_V3_RX_DELAY_MASK
> > - CLK_V2_ALWAYS_ON / CLK_V3_ALWAYS_ON
> > 
> > are these used for the MMC clock or are some of these routed to the
> > NAND pins as well?
> 
> There clocks are not used in NAND driver..
> 
> I understand your concern here, if there clocks are also routed to NAND
> pins, then we also need to implement them here
> actually, to answer your question, I need to query the ASIC team..

Even if the NAND driver does not need to change the phases, it might need to
make sure these phases are reset on init. It would not hurt to handle these
phases in your clock controller.