lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Wed, 4 Jul 2018 09:22:55 -0500 From: "Gustavo A. R. Silva" <gustavo@...eddedor.com> To: Eric Anholt <eric@...olt.net>, David Airlie <airlied@...ux.ie> Cc: dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org, "Gustavo A. R. Silva" <gustavo@...eddedor.com> Subject: [PATCH v2] drm/pl111: Use 64-bit arithmetic instead of 32-bit Add suffix ULL to constant 1000 in order to give the compiler complete information about the proper arithmetic to use. Notice that such constant is used in a context that expects an expression of type u64 (64 bits, unsigned) and the following expression is currently being evaluated using 32-bit arithmetic: mode->clock * 1000 Addresses-Coverity-ID: 1466139 ("Unintentional integer overflow") Signed-off-by: Gustavo A. R. Silva <gustavo@...eddedor.com> --- Changes in v2: - Use suffix ULL instead of UL. drivers/gpu/drm/pl111/pl111_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index a432eb7..754f6b2 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -63,7 +63,7 @@ pl111_mode_valid(struct drm_crtc *crtc, * We use the pixelclock to also account for interlaced modes, the * resulting bandwidth is in bytes per second. */ - bw = mode->clock * 1000; /* In Hz */ + bw = mode->clock * 1000ULL; /* In Hz */ bw = bw * mode->hdisplay * mode->vdisplay * cpp; bw = div_u64(bw, mode->htotal * mode->vtotal); -- 2.7.4
Powered by blists - more mailing lists