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Message-ID: <153092054581.143105.16123786121344421693@swboyd.mtv.corp.google.com>
Date: Fri, 06 Jul 2018 16:42:25 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
Taniya Das <tdas@...eaurora.org>
Cc: Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
Rajendra Nayak <rnayak@...eaurora.org>,
Amit Nischal <anischal@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
rohitkr@...eaurora.org, Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH v2 1/2] dt-bindings: clock: Introduce QCOM LPASS clock bindings
Quoting Taniya Das (2018-07-04 23:55:20)
> diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
> new file mode 100644
> index 0000000..fe7378b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
> @@ -0,0 +1,22 @@
> +Qualcomm LPASS Clock Controller Binding
> +-----------------------------------------------
> +
> +Required properties :
> +- compatible : shall contain "qcom,sdm845-lpasscc"
> +- #clock-cells : from common clock binding, shall contain 1.
> +- reg : shall contain base register address and size.
> +- reg-names : shall contain the register names of LPASS domain
> + "lpass_gcc", "lpass_cc", "lpass_qdsp6ss".
> +
> +Example:
> +
> +The below node has to be defined in the cases where the LPASS peripheral loader
> +would bring the subsystem out of reset.
> +
> + lpasscc: clock-controller {
> + compatible = "qcom,sdm845-lpasscc";
> + reg = <0x00147000 0x20>, <0x17014000 0x1f004>,
This first reg is inside GCC though? Why isn't it added to the gcc
sdm845 driver? And then the next two might make sense as a different
region, but the reg property ending in 20 looks really weird.
> + <0x17300020 0x20>;
> + reg-names = "lpass_gcc", "lpass_cc", "lpass_qdsp6ss";
> + #clock-cells = <1>;
> + };
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