linux-kernel - Re: [PATCH V2 16/19] csky: SMP support

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Message-ID: <20180706132215.GB30265@guoren>
Date:   Fri, 6 Jul 2018 21:22:15 +0800
From:   Guo Ren <ren_guo@...ky.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
        tglx@...utronix.de, daniel.lezcano@...aro.org,
        jason@...edaemon.net, arnd@...db.de, c-sky_gcc_upstream@...ky.com,
        gnu-csky@...tor.com, thomas.petazzoni@...tlin.com,
        wbx@...ibc-ng.org, green.hu@...il.com,
        Will Deacon <will.deacon@....com>
Subject: Re: [PATCH V2 16/19] csky: SMP support

On Fri, Jul 06, 2018 at 11:39:32AM +0200, Peter Zijlstra wrote:
> On Fri, Jul 06, 2018 at 02:07:40PM +0800, Guo Ren wrote:
> 
> > > Please explain those mb()'s... I'm thinking you meant to use smp_mb().
> > Yes, smp_mb(). Current smp_mb()&mb() is the same: sync.is.
> > 
> > In next version patch, I'll seperate smp_mb() and mb() and use ld/st.barrier
> > instead of sync.is. Sync.is is expensive that it flush cpu's pipeline.
> 
> I'll second my own call for documentation, because now there's three
> memory ordering instructions:
> 
>  "SYNC", "SYNC.IS" and "LD/ST.BARRIER"
> 
> None of which have yet been explained.
In C-SKY there are:

sync:        completion barrier
sync.s:      completion barrier and shareable to other cores
sync.i:      completion barrier with flush cpu pipeline
sync.is:     completion barrier with flush cpu pipeline and shareable to other cores 

bar.brwarw:  ordering barrier for all load/store instructions before it
bar.brwarws: ordering barrier for all load/store instructions before it and shareable to other cores
bar.brar:    ordering barrier for all load       instructions before it
bar.brars:   ordering barrier for all load       instructions before it and shareable to other cores
bar.bwaw:    ordering barrier for all store      instructions before it
bar.bwaws:   ordering barrier for all store      instructions before it and shareable to other cores