[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <153090935492.143105.6442521447151039533@swboyd.mtv.corp.google.com>
Date: Fri, 06 Jul 2018 13:35:54 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
Paul Cercueil <paul@...pouillou.net>
Cc: Paul Burton <paul.burton@...s.com>,
James Hogan <jhogan@...nel.org>, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Paul Cercueil <paul@...pouillou.net>
Subject: Re: [PATCH 2/2] clk: ingenic: Add missing flag for UDC clock
Quoting Paul Cercueil (2018-06-27 05:14:59)
> The UDC clock of the JZ4740 SoC can be gated, but the data structure
> representing it was missing the CGU_CLK_GATE flag to make it work.
>
> Signed-off-by: Paul Cercueil <paul@...pouillou.net>
> ---
Applied to clk-next
Powered by blists - more mailing lists