linux-kernel - Re: [PATCH 1/2] clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz

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Message-ID: <87va9oct5k.fsf@bootlin.com>
Date:   Mon, 09 Jul 2018 17:42:31 +0200
From:   Gregory CLEMENT <gregory.clement@...tlin.com>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Mike Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, Andrew Lunn <andrew@...n.ch>,
        Jason Cooper <jason@...edaemon.net>,
        Hua Jing <jinghua@...vell.com>,
        Antoine Tenart <antoine.tenart@...tlin.com>,
        stable@...r.kernel.org,
        Maxime Chevallier <maxime.chevallier@...tlin.com>,
        Nadav Haklai <nadavh@...vell.com>, Ken Ma <make@...vell.com>,
        Victor Gu <xigu@...vell.com>,
        Neta Zur Hershkovits <neta@...vell.com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Miquèl Raynal <miquel.raynal@...tlin.com>,
        Marcin Wojtas <mw@...ihalf.com>,
        Wilson Ding <dingwei@...vell.com>,
        linux-arm-kernel@...ts.infradead.org,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
Subject: Re: [PATCH 1/2] clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz

Hi Stephen,
 
 On ven., juil. 06 2018, Stephen Boyd <sboyd@...nel.org> wrote:

> Quoting Gregory CLEMENT (2018-06-29 07:44:02)
>> Hi,
>>  
>>  On mar., juin 19 2018, Gregory CLEMENT <gregory.clement@...tlin.com> wrote:
>> 
>> > Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
>> > respectively) to L0 frequency (1.2 Ghz) requires a significant amount
>> > of time to let VDD stabilize to the appropriate voltage. This amount of
>> > time is large enough that it cannot be covered by the hardware
>> > countdown register. Due to this, the CPU might start operating at L0
>> > before the voltage is stabilized, leading to CPU stalls.
>> >
>> > To work around this problem, we prevent switching directly from the
>> > L2/L3 frequencies to the L0 frequency, and instead switch to the L1
>> > frequency in-between. The sequence therefore becomes:
>> >
>> > 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
>> > 2. Sleep 20ms for stabling VDD voltage
>> > 3. Then switch from L1(600MHZ) to L0(1200Mhz).
>> 
>> Do you have any comment on this fix?
>> 
>
> Looks good. Is it crashing right now? I can throw it into clk-fixes if
> it's fixing pain.

Yes for the SoC capable to run at 1200Mhz it crashes. At the time the
initial support was provided, my SoC version only ran at 1000MHz, so the
problem was not noticed.

Thanks,

Gregory


-- 
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com