linux-kernel - Re: [PATCH v2 1/4] x86/split_lock: Enumerate #AC exception for split locked access feature

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Message-ID: <alpine.DEB.2.21.1807102140050.1588@nanos.tec.linutronix.de>
Date:   Tue, 10 Jul 2018 21:47:26 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Dave Hansen <dave.hansen@...el.com>
cc:     Fenghua Yu <fenghua.yu@...el.com>,
        Eduardo Habkost <ehabkost@...hat.com>,
        Ingo Molnar <mingo@...hat.com>, H Peter Anvin <hpa@...or.com>,
        Ashok Raj <ashok.raj@...el.com>,
        Alan Cox <alan@...ux.intel.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Rafael Wysocki <rafael.j.wysocki@...el.com>,
        Tony Luck <tony.luck@...el.com>,
        Ravi V Shankar <ravi.v.shankar@...el.com>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        x86 <x86@...nel.org>,
        Vedvyas Shanbhogue <vedvyas.shanbhogue@...el.com>
Subject: Re: [PATCH v2 1/4] x86/split_lock: Enumerate #AC exception for split
 locked access feature

On Tue, 10 Jul 2018, Dave Hansen wrote:
> On 07/10/2018 11:45 AM, Fenghua Yu wrote:
> > On Wed, Jul 04, 2018 at 05:07:42PM -0300, Eduardo Habkost wrote:
> >> On Fri, Jun 29, 2018 at 06:23:35PM +0200, Thomas Gleixner wrote:
> >>> On Fri, 29 Jun 2018, Dave Hansen wrote:
> >>>> Is this MSR not really model-specific?  Is it OK to go poking at it on
> >>>> all x86 variants?  Or, do we at _least_ need a check for Intel cpus in here?
> >>>
> >>> That definitely needs a vendor check. Also the whole code needs to be
> >>> compiled out if CONFIG_INTEL=n.
> >>>
> >>> Aside of that this wants to be enumerated. CPUID or MISC_FEATURES and not
> >>> this guess work detection logic. Why do I have to ask for that for every
> >>> other new feature thingy?
> >>
> >> Yes, please.  KVM hosts normally expect guests to not touch MSRs
> >> unless we explicitly tell them the MSR is available (normally
> >> through CPUID).  This is important to ensure live migration
> >> between different host kernel versions works reliably.
> > 
> > The problem is the hardware design for the feature is complete. The
> > hardware designer cannot change the feature enumeration to CPUID or
> > MISC_FEATURES.

Setting a fricking bit in a CPUID leaf or in a MSR cannot be done anymore?
That's just hilarious.

> Let's be honest, though.  That's not *hardware* design; that is a
> microcode update.  We've seen what microcode updates can do _very_
> clearly with all the security issues.  We (Intel) can surely fix this if
> sufficiently motivated.  No?

Amen to that.

And please tell your hardware people that they should stop creating
features which are not enumerated in one way or the other. That's just a
pain all over the place. Boot code, kernel, virt, tools ....

Thanks,

	tglx