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Date:   Tue, 10 Jul 2018 23:19:45 +0200
From:   Boris Brezillon <boris.brezillon@...tlin.com>
To:     Girish Mahadevan <girishm@...eaurora.org>
Cc:     broonie@...nel.org, linux-spi@...r.kernel.org,
        linux-kernel@...r.kernel.org, dianders@...omium.org,
        swboyd@...omium.org, linux-arm-msm@...r.kernel.org,
        sdharia@...eaurora.org, kramasub@...eaurora.org
Subject: Re: [PATCH 2/2] spi: Introduce new driver for Qualcomm QuadSPI
 controller

Hi Girish,

On Thu,  5 Jul 2018 15:46:42 -0600
Girish Mahadevan <girishm@...eaurora.org> wrote:

> +
> +static int process_data(const struct spi_mem_op *op, struct qcom_qspi *ctrl)
> +{
> +	int ret;
> +
> +	ctrl->xfer.dir = (op->data.dir == SPI_MEM_DATA_IN) ?
> +					QSPI_READ : QSPI_WRITE;
> +	ctrl->xfer.mode = op->data.buswidth;
> +	ctrl->xfer.is_last = true;
> +	ctrl->xfer.rem_bytes = op->data.nbytes;
> +
> +	if (ctrl->xfer.dir == QSPI_WRITE)
> +		ctrl->xfer.tx_buf = op->data.buf.out;
> +	else
> +		ctrl->xfer.rx_buf = op->data.buf.in;
> +	ret = qcom_qspi_pio_xfer(ctrl);
> +	if (ret)
> +		return ret;

Looks like you are converting the spi_mem_op into several regular SPI
transfers. Any good reasons for not relying on the core logic to do
that? In this case, all you'd have to do is implement ->transfer_one()
and be done with it. 

> +	ret = wait_for_xfer(ctrl);
> +	return ret;
> +}
 
Regards,

Boris

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