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Message-ID: <CACPK8Xf7mCuksfgH4jfxcgbT2h0-WH236=pWchzbucrrVsLF3A@mail.gmail.com>
Date: Wed, 11 Jul 2018 14:29:03 +1000
From: Joel Stanley <joel@....id.au>
To: Eddie James <eajames@...ux.vnet.ibm.com>
Cc: Wolfram Sang <wsa@...-dreams.de>, linux-i2c@...r.kernel.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
devicetree <devicetree@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Mark Rutland <mark.rutland@....com>,
Greg KH <gregkh@...uxfoundation.org>,
Randy Dunlap <rdunlap@...radead.org>,
Andy Shevchenko <andy.shevchenko@...il.com>,
Peter Rosin <peda@...ntia.se>
Subject: Re: [PATCH v11 5/8] i2c: fsi: Add transfer implementation
On 11 July 2018 at 06:59, Eddie James <eajames@...ux.vnet.ibm.com> wrote:
>
>
> On 07/10/2018 02:39 PM, Wolfram Sang wrote:
>>>
>>> Sorry, what do you mean "show up as"? Yes, we could first shift all our
>>> addresses in user-space before passing them to the driver, so that the
>>> msg->addr field is exactly what the hardware expects already... This
>>> would
>>> be non-trivial for our users considering all our documentation represents
>>> the addresses as the top 7 bits of a byte :(
>>
>> Ah, now I understand the whole situation! Good that I asked. But I have
>> bad news for you:
>>
>> msg->addr is 7 bit and LSB aligned. No way around that. This is how
>> Linux I2C worked since the beginning. You have to adapt to it.
>>
>> I know what you mean. Most doumentation I get has the addresses in 8
>> bit, i.e. 7 bit address shifted + RW bit. But sorry again, the Linux
>> representation is different and all drivers have to adhere to that.
>>
>> An EEPROM ist at 0x50 in Linux. There is no write addr 0xa0 and read
>> addr 0xa1.
>
>
> OK, I understand! Will test and resend with conforming addressing. Thanks
> for all the feedback!
Nice one Wolfram. I wondered why the standard tools didn't work, but
hadn't gotten around to working out what was going on.
Thanks for taking a close look.
Cheers,
Joel
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