linux-kernel - Re: [PATCH V2] MIPS: implement smp_cond_load

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Message-ID: <20180711105546.GB2476@hirez.programming.kicks-ass.net>
Date:   Wed, 11 Jul 2018 12:55:46 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     David Laight <David.Laight@...LAB.COM>
Cc:     'Paul Burton' <paul.burton@...s.com>,
        陈华才 <chenhc@...ote.com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        James Hogan <jhogan@...nel.org>,
        linux-mips <linux-mips@...ux-mips.org>,
        Fuxin Zhang <zhangfx@...ote.com>,
        wuzhangjin <wuzhangjin@...il.com>,
        stable <stable@...r.kernel.org>,
        Alan Stern <stern@...land.harvard.edu>,
        Andrea Parri <andrea.parri@...rulasolutions.com>,
        Will Deacon <will.deacon@....com>,
        Boqun Feng <boqun.feng@...il.com>,
        Nicholas Piggin <npiggin@...il.com>,
        David Howells <dhowells@...hat.com>,
        Jade Alglave <j.alglave@....ac.uk>,
        Luc Maranget <luc.maranget@...ia.fr>,
        "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
        Akira Yokosawa <akiyks@...il.com>,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2] MIPS: implement smp_cond_load_acquire() for Loongson-3

On Wed, Jul 11, 2018 at 10:04:52AM +0000, David Laight wrote:
> I also suspect that 'write starvation' is also common - after all the
> purpose of the store buffer is to do reads in preference to writes in
> order to reduce the cpu stalls waiting for the memory bus (probably
> the cpu to cache interface).
> 
> I think your example is just:
> 	*(volatile int *)xxx = 1;
> 	while (!*(volatile int *)yyy) continue;
> running on two cpu with xxx and yyy swapped?

Yep. And Linux has been relying on that working for (afaict) basically
forever.

> You need a stronger bus cycle in there somewhere.

Since all spin-wait loops _should_ have cpu_relax() that is the natural
place to put it.