linux-kernel - [PATCH] nand: ranw: qcom_nand: stop using phys_to

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Message-Id: <20180711122709.358159-1-arnd@arndb.de>
Date:   Wed, 11 Jul 2018 14:26:58 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Boris Brezillon <boris.brezillon@...tlin.com>,
        Miquel Raynal <miquel.raynal@...tlin.com>,
        David Woodhouse <dwmw2@...radead.org>,
        Brian Norris <computersforpeace@...il.com>,
        Marek Vasut <marek.vasut@...il.com>,
        Richard Weinberger <richard@....at>,
        Abhishek Sahu <absahu@...eaurora.org>
Cc:     Arnd Bergmann <arnd@...db.de>,
        Archit Taneja <architt@...eaurora.org>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH] nand: ranw: qcom_nand: stop using phys_to_dma()

Compile-testing this driver on x86 caused a link error:

ERROR: "__phys_to_dma" [drivers/mtd/nand/raw/qcom_nandc.ko] undefined!

The problem here is that the driver attempts to convert the physical
address into the DMA controller as a dma_addr_t and calls phys_to_dma()
to do the conversion.

However, there is no generic way to convert a phys_addr_t into a dma_addr_t
for anything other than RAM (which should use the dma-mapping API instead).
The only correct use of phys_to_dma() instead is inside of the dma-mapping
implementation.

In all other drivers that deal with DMA FIFO addresses, we just pass the
physical address directly and have the DMA controller deal with that
if necessary, so let's do the same thing here.

Fixes: c76b78d8ec05 ("mtd: nand: Qualcomm NAND controller driver")
Signed-off-by: Arnd Bergmann <arnd@...db.de>
---
 drivers/mtd/nand/raw/qcom_nandc.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 994f980c6d86..f047e2819041 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -338,7 +338,6 @@ struct nandc_regs {
  * @dev:			parent device
  * @base:			MMIO base
  * @base_phys:			physical base address of controller registers
- * @base_dma:			dma base address of controller registers
  * @core_clk:			controller clock
  * @aon_clk:			another controller clock
  *
@@ -372,7 +371,6 @@ struct qcom_nand_controller {
 
 	void __iomem *base;
 	phys_addr_t base_phys;
-	dma_addr_t base_dma;
 
 	struct clk *core_clk;
 	struct clk *aon_clk;
@@ -935,11 +933,11 @@ static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
 	slave_conf.device_fc = flow_control;
 	if (read) {
 		slave_conf.src_maxburst = 16;
-		slave_conf.src_addr = nandc->base_dma + reg_off;
+		slave_conf.src_addr = (dma_addr_t)nandc->base_phys + reg_off;
 		slave_conf.slave_id = nandc->data_crci;
 	} else {
 		slave_conf.dst_maxburst = 16;
-		slave_conf.dst_addr = nandc->base_dma + reg_off;
+		slave_conf.dst_addr = (dma_addr_t)nandc->base_phys + reg_off;
 		slave_conf.slave_id = nandc->cmd_crci;
 	}
 
@@ -2963,7 +2961,6 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 		return PTR_ERR(nandc->base);
 
 	nandc->base_phys = res->start;
-	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
 
 	nandc->core_clk = devm_clk_get(dev, "core");
 	if (IS_ERR(nandc->core_clk))
-- 
2.9.0