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Message-ID: <d502fe124cb7ba447c81a2a76b925aff@codeaurora.org>
Date: Thu, 12 Jul 2018 18:02:25 +0530
From: Amit Nischal <anischal@...eaurora.org>
To: Stephen Boyd <sboyd@...nel.org>
Cc: Michael Turquette <mturquette@...libre.com>,
Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
Rajendra Nayak <rnayak@...eaurora.org>,
Odelu Kukatla <okukatla@...eaurora.org>,
Taniya Das <tdas@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk-owner@...r.kernel.org
Subject: Re: [PATCH 3/4] dt-bindings: clock: Introduce QCOM Graphics clock
bindings
On 2018-07-09 11:08, Stephen Boyd wrote:
> Quoting Amit Nischal (2018-06-06 04:41:47)
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
>> b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
>> new file mode 100644
>> index 0000000..e311219
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
>> @@ -0,0 +1,18 @@
>> +Qualcomm Graphics Clock & Reset Controller Binding
>> +--------------------------------------------------
>> +
>> +Required properties :
>> +- compatible : shall contain "qcom,sdm845-gpucc".
>> +- reg : shall contain base register location and length.
>> +- #clock-cells : from common clock binding, shall contain 1.
>> +- #reset-cells : from common reset binding, shall contain 1.
>> +- #power-domain-cells : from generic power domain binding, shall
>> contain 1.
>> +
>> +Example:
>> + gpucc: clock-controller@@5090000 {
>
> Drop the double '@'
Oh. I will fix this in next patch series.
>
>> + compatible = "qcom,sdm845-gpucc";
>> + reg = <0x5090000 0x9000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
> --
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