linux-kernel - Re: [RESEND PATCH] mmc: tegra: enable ddr_signaling for MMC_TIMING_MMC

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Date:   Thu, 12 Jul 2018 20:28:49 +0000
From:   Marcel Ziswiler <marcel.ziswiler@...adex.com>
To:     "tszucs@...tonmail.ch" <tszucs@...tonmail.ch>,
        "ulf.hansson@...aro.org" <ulf.hansson@...aro.org>,
        "adrian.hunter@...el.com" <adrian.hunter@...el.com>
CC:     "jonathanh@...dia.com" <jonathanh@...dia.com>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "thierry.reding@...il.com" <thierry.reding@...il.com>,
        "linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>
Subject: Re: [RESEND PATCH] mmc: tegra: enable ddr_signaling for
 MMC_TIMING_MMC_DDR52

On Thu, 2018-07-12 at 19:38 +0200, Tamás Szűcs wrote:
> This fixes sampling errors with eMMC modules using DDR52 when host
> capabilities
> via setting NVQUIRK_ENABLE_DDR50 and NVQUIRK_ENABLE_SDHCI_SPEC_300
> are enabled.
> 
> Signed-off-by: Tamás Szűcs <tszucs@...tonmail.ch>
> ---
>  drivers/mmc/host/sdhci-tegra.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-
> tegra.c
> index 970d38f68939..a3bfaa7067c8 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -228,7 +228,7 @@ static void tegra_sdhci_set_uhs_signaling(struct
> sdhci_host *host,
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>  	struct sdhci_tegra *tegra_host =
> sdhci_pltfm_priv(pltfm_host);
>  
> -	if (timing == MMC_TIMING_UHS_DDR50)
> +	if (timing == MMC_TIMING_UHS_DDR50 || timing ==
> MMC_TIMING_MMC_DDR52)
>  		tegra_host->ddr_signaling = true;
>  
>  	sdhci_set_uhs_signaling(host, timing);

This is really a duplicate of Stefan's "[PATCH 2/3] mmc: tegra: fix eMMC DDR52
mode" [1] resp. Stefan's is a duplicate of Tamás'. We missed it as it somehow
bounced the tegra mailing list. We basically investigated this upon Tamás'
request (u-blox being our customer) more or less in parallel.

[1] https://lore.kernel.org/lkml/20180712073904.4705-2-stefan@agner.ch