linux-kernel - Re: [PATCH] mmc: tegra: Add and use tegra_sdhci_get_max

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Date:   Fri, 13 Jul 2018 15:42:36 +0000
From:   Marcel Ziswiler <marcel.ziswiler@...adex.com>
To:     "ulf.hansson@...aro.org" <ulf.hansson@...aro.org>,
        "avienamo@...dia.com" <avienamo@...dia.com>,
        "jonathanh@...dia.com" <jonathanh@...dia.com>,
        "thierry.reding@...il.com" <thierry.reding@...il.com>,
        "adrian.hunter@...el.com" <adrian.hunter@...el.com>
CC:     "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
        Stefan Agner <stefan.agner@...adex.com>
Subject: Re: [PATCH] mmc: tegra: Add and use tegra_sdhci_get_max_clock()

On Fri, 2018-07-13 at 16:17 +0300, Aapo Vienamo wrote:
> Implement and use tegra_sdhci_get_max_clock() which returns the true
> maximum host clock rate. The issue with tegra_sdhci_get_max_clock()
> is
> that it returns the current clock rate of the host instead of the
> maximum one, which can lead to unnecessarily small clock rates.
> 
> This differs from the previous implementation of
> tegra_sdhci_get_max_clock() in that it doesn't divide the result by
> two.
> 
> Signed-off-by: Aapo Vienamo <avienamo@...dia.com>

The whole series stress-tested on various Apalis T30 as well as Colibri
T30 modules:

Tested-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>

> ---
>  drivers/mmc/host/sdhci-tegra.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-
> tegra.c
> index 28b98e2..ddf00166 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -235,6 +235,13 @@ static void tegra_sdhci_set_uhs_signaling(struct
> sdhci_host *host,
>  	sdhci_set_uhs_signaling(host, timing);
>  }
>  
> +static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host
> *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +
> +	return clk_round_rate(pltfm_host->clk, UINT_MAX);
> +}
> +
>  static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned
> int tap)
>  {
>  	u32 reg;
> @@ -299,7 +306,7 @@ static const struct sdhci_ops tegra_sdhci_ops = {
>  	.platform_execute_tuning = tegra_sdhci_execute_tuning,
>  	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
>  	.voltage_switch = tegra_sdhci_voltage_switch,
> -	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
> +	.get_max_clock = tegra_sdhci_get_max_clock,
>  };
>  
>  static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
> @@ -356,7 +363,7 @@ static const struct sdhci_ops tegra114_sdhci_ops
> = {
>  	.platform_execute_tuning = tegra_sdhci_execute_tuning,
>  	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
>  	.voltage_switch = tegra_sdhci_voltage_switch,
> -	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
> +	.get_max_clock = tegra_sdhci_get_max_clock,
>  };
>  
>  static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {

Works quite nicely on today's next together with Stefan's patch set [1]:

root@...lis-t30:~# cat /sys/kernel/debug/mmc1/ios 
clock:          52000000 Hz
actual clock:   51000000 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    8 (mmc DDR52)
signal voltage: 1 (1.80 V)
driver type:    0 (driver type B)
root@...lis-t30:~# hdparm -t /dev/mmcblk1

/dev/mmcblk1:
 Timing buffered disk reads: 236 MB in  3.01 seconds =  78.42 MB/sec

root@...ibri-t30:~# cat /sys/kernel/debug/mmc0/ios 
clock:          52000000 Hz
actual clock:   51000000 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    8 (mmc DDR52)
signal voltage: 1 (1.80 V)
driver type:    0 (driver type B)
root@...ibri-t30:~# hdparm -t /dev/mmcblk0

/dev/mmcblk0:
 Timing buffered disk reads: 168 MB in  3.00 seconds =  55.99 MB/sec

[1] https://lore.kernel.org/lkml/20180712073904.4705-1-stefan@agner.ch