linux-kernel - Re: [PATCH 6/6] coresight: etm-perf: Add support for ETR backend

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Message-ID: <CANLsYkzMoU=9JibeuK6dUrK+umxPEuFaYyEStY5h2p=V5ujBUA@mail.gmail.com>
Date:   Mon, 16 Jul 2018 09:05:43 -0600
From:   Mathieu Poirier <mathieu.poirier@...aro.org>
To:     "Suzuki K. Poulose" <Suzuki.Poulose@....com>
Cc:     linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        coresight@...ts.linaro.org, Robert Walker <robert.walker@....com>,
        Mike Leach <mike.leach@...aro.org>
Subject: Re: [PATCH 6/6] coresight: etm-perf: Add support for ETR backend

On Fri, 13 Jul 2018 at 05:23, Suzuki K Poulose <Suzuki.Poulose@....com> wrote:
>
> On 12/07/18 21:57, Mathieu Poirier wrote:
> > Hi Suzuki,
> >
> > On Wed, Jul 11, 2018 at 03:16:39PM +0100, Suzuki K Poulose wrote:
> >> Add support for using TMC-ETR as backend for ETM perf tracing.
> >> We use software double buffering at the moment. i.e, the TMC-ETR
> >> uses a separate buffer than the perf ring buffer. The data is
> >> copied to the perf ring buffer once a session completes.
> >>
> >> The TMC-ETR would try to match the larger of perf ring buffer
> >> or the ETR buffer size configured via sysfs, scaling down to
> >> a minimum limit of 1MB.
> >>
> >> Cc: Mathieu Poirier <mathieu.poirier@...aro.org>
> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@....com>
> >> ---
> >>   drivers/hwtracing/coresight/coresight-tmc-etr.c | 265 +++++++++++++++++++++++-
> >>   drivers/hwtracing/coresight/coresight-tmc.h     |   2 +
> >>   2 files changed, 265 insertions(+), 2 deletions(-)
>
> >> +/*
> >> + * tmc_etr_sync_perf_buffer: Copy the actual trace data from the hardware
> >> + * buffer to the perf ring buffer.
> >> + */
> >> +static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
> >> +{
> >> +    long bytes, to_copy;
> >> +    long pg_idx, pg_offset, src_offset;
> >> +    unsigned long head = etr_perf->head;
> >> +    char **dst_pages, *src_buf;
> >> +    struct etr_buf *etr_buf = etr_perf->etr_buf;
> >> +
> >> +    head = PERF_IDX2OFF(etr_perf->head, etr_perf);
> >
> > I'm puzzled here.  Since etr_perf->head is set in tmc_etr_set_perf_buffer() to
> > the value of handle->head, its value is always within the range of the perf ring
>
> IIUC, the handle->head is not necessarily guaranteed to be within the aux-ring buffer.

I just looked at the ETB code and you are correct.

>
> > buffer.  In tmc_etr_alloc_perf_buffer() etr_perf->nr_pages is set to the number
> > of pages present in that ring buffer.  As such I'm not sure as to why we need
> > the PERF_IDX2OFF() macro.
> >
> > It seems to me that "head = etr_perf->head;" above is sufficient.
> >
>
> We need to do the step at some point, which could be moved to set_perf_buffer.

That's a good idea.

>
> >> +    pg_idx = head >> PAGE_SHIFT;
> >> +    pg_offset = head & (PAGE_SIZE - 1);
> >> +    dst_pages = (char **)etr_perf->pages;
> >> +    src_offset = etr_buf->offset;
> >> +    to_copy = etr_buf->len;
> >> +
> >> +    while (to_copy > 0) {
> >> +            /*
> >> +             * We can copy minimum of :
> >
> > s/We can copy minimum of :/In one iteration we can copy a minimum of:/
> >
> > If I'm wrong about the PERF_IDX2OFF(), don't bother respinning just for that.
>
> I have some more fixes for handling the different modes (sysfs vs perf),
> which I can include in the v2.

Very well.

>
> Suzuki