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Message-Id: <20180717195242.GV12945@linux.vnet.ibm.com>
Date: Tue, 17 Jul 2018 12:52:42 -0700
From: "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
To: Andrea Parri <andrea.parri@...rulasolutions.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>,
Michael Ellerman <mpe@...erman.id.au>,
Peter Zijlstra <peterz@...radead.org>,
Alan Stern <stern@...land.harvard.edu>,
Will Deacon <will.deacon@....com>,
Akira Yokosawa <akiyks@...il.com>,
Boqun Feng <boqun.feng@...il.com>,
Daniel Lustig <dlustig@...dia.com>,
David Howells <dhowells@...hat.com>,
Jade Alglave <j.alglave@....ac.uk>,
Luc Maranget <luc.maranget@...ia.fr>,
Nick Piggin <npiggin@...il.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] tools/memory-model: Add extra ordering for locks and
remove it for ordinary release/acquire
On Tue, Jul 17, 2018 at 09:40:01PM +0200, Andrea Parri wrote:
> > > That said, I don't understand the powerpc memory ordering. I thought
> > > the rules were "isync on lock, lwsync on unlock".
> > >
> > > That's what the AIX docs imply, at least.
> > >
> > > In particular, I find:
> > >
> > > "isync is not a memory barrier instruction, but the
> > > load-compare-conditional branch-isync sequence can provide this
> > > ordering property"
> > >
> > > so why are you doing "sync/lwsync", when it sounds like "isync/lwsync"
> > > (for lock/unlock) is the right thing and would already give memory
> > > barrier semantics?
> >
> > The PowerPC guys will correct me if I miss something here...
>
> [Same here.]
>
> > The isync provides ordering roughly similar to lwsync, but nowhere near
> > as strong as sync, and it is sync that would be needed to cause lock
> > acquisition to provide full ordering.
>
> IIRC, ctrl+isync is even *weaker* than lwsync in certain respects, e.g.,
> the former doesn't provide A-cumulativity according to the architectural
> intent.
>
>
> >The reason for using lwsync instead
> > of isync is that the former proved to be faster on recent hardware.
>
> Interesting; can you add some references about this?
Sadly, no. I just asked why all the isyncs were being rewritten by
lwsyncs some years back, and that is the answer I got. I trust the
people answering, so didn't dig further.
Thanx, Paul
> Andrea
>
>
> > The reason that the kernel still has the ability to instead generate
> > isync instructions is that some older PowerPC hardware does not provide
> > the lwsync instruction. If the hardware does support lwsync, the isync
> > instructions are overwritten with lwsync at boot time.
> >
> > Thanx, Paul
> >
>
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