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Message-ID: <CAHp75Vcvqqv4kHHDE2wbtVFFa3a5FLqg8meDeOa59-qaDFGFTw@mail.gmail.com>
Date: Wed, 18 Jul 2018 00:34:37 +0300
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Alexandre Belloni <alexandre.belloni@...tlin.com>
Cc: Mark Brown <broonie@...nel.org>, James Hogan <jhogan@...nel.org>,
Paul Burton <paul.burton@...s.com>,
linux-spi <linux-spi@...r.kernel.org>,
devicetree <devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Linux MIPS Mailing List <linux-mips@...ux-mips.org>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Allan Nielsen <allan.nielsen@...rosemi.com>,
Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH 3/5] spi: dw-mmio: add MSCC Ocelot support
On Tue, Jul 17, 2018 at 5:23 PM, Alexandre Belloni
<alexandre.belloni@...tlin.com> wrote:
> Because the SPI controller deasserts the chip select when the TX fifo is
> empty (which may happen in the middle of a transfer), the CS should be
> handled by linux. Unfortunately, some or all of the first four chip
> selects are not muxable as GPIOs, depending on the SoC.
>
> There is a way to bitbang those pins by using the SPI boot controller so
> use it to set the chip selects.
>
> At init time, it is also necessary to give control of the SPI interface to
> the Designware IP.
> + ret = dw_spi_mscc_init(pdev, dwsmmio);
> + if (ret)
> + goto out;
> + { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_init},
Looks like you were thinking about something like
init_func = device_get_match_data(...);
if (init_func) {
ret = init_func();
if (ret)
return ret;
}
?
--
With Best Regards,
Andy Shevchenko
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