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Message-ID: <070b9fec-a66a-9f2e-bef4-22eaa6d6ddf3@gmail.com>
Date:   Tue, 17 Jul 2018 09:56:34 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Ryder Lee <ryder.lee@...iatek.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Sean Wang <sean.wang@...iatek.com>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v1 2/2] arm64: dts: mt7622: update a clock property for
 UART0



On 16/07/18 16:59, Ryder Lee wrote:
> The input clock of UART0 should be CLK_PERI_UART0_PD.
> 
> Fixes: 13f36c326cef ("arm64: dts: mt7622: turn uart0 clock to real ones")
> Signed-off-by: Ryder Lee <ryder.lee@...iatek.com>
> ---

pused to v4.18-next/dts64

Thanks a lot!

> change since v1:
> - add Fixes tag.
> ---
>  arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index 8cdec52..4caa9b4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -367,7 +367,7 @@
>  		reg = <0 0x11002000 0 0x400>;
>  		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
>  		clocks = <&topckgen CLK_TOP_UART_SEL>,
> -			 <&pericfg CLK_PERI_UART1_PD>;
> +			 <&pericfg CLK_PERI_UART0_PD>;
>  		clock-names = "baud", "bus";
>  		status = "disabled";
>  	};
> 

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