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Message-Id: <20180717153643.8806-9-jbrunet@baylibre.com>
Date: Tue, 17 Jul 2018 17:36:32 +0200
From: Jerome Brunet <jbrunet@...libre.com>
To: Mark Brown <broonie@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>,
Kevin Hilman <khilman@...libre.com>,
Carlo Caione <carlo@...one.org>
Cc: Jerome Brunet <jbrunet@...libre.com>, alsa-devel@...a-project.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-amlogic@...ts.infradead.org
Subject: [PATCH 07/15] ASoC: meson: add axg tdm formatters DT binding documentation
Add the DT binding documentation for axg's TDM formatters: TDMIN
and TDMOUT.
Signed-off-by: Jerome Brunet <jbrunet@...libre.com>
---
.../bindings/sound/amlogic,axg-tdm-formatters.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt
diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt
new file mode 100644
index 000000000000..1c1b7490554e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt
@@ -0,0 +1,28 @@
+* Amlogic Audio TDM formatters
+
+Required properties:
+- compatible: 'amlogic,axg-tdmin' or
+ 'amlogic,axg-tdmout'
+- reg: physical base address of the controller and length of memory
+ mapped region.
+- clocks: list of clock phandle, one for each entry clock-names.
+- clock-names: should contain the following:
+ * "pclk" : peripheral clock.
+ * "sclk" : bit clock.
+ * "sclk_sel" : bit clock input multiplexer.
+ * "lrclk" : sample clock
+ * "lrclk_sel": sample clock input multiplexer
+
+Example of TDMOUT_A on the A113 SoC:
+
+tdmout_a: audio-controller@500 {
+ compatible = "amlogic,axg-tdmout";
+ reg = <0x0 0x500 0x0 0x40>;
+ clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+};
--
2.14.4
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